EPM5192GC-2 vs EPM5192LC-1 Comparison
Detailed side-by-side comparison of EPM5192GC-2 by Altera and EPM5192LC-1 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GC-2 | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | — |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | — |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | — |
| Counter Frequency | 100 MHz minimum | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Technology | CMOS EPROM | CMOS, UV-erasable / OTP EPROM cell |
| Programmable Technology | UV-erasable / one-time programmable | — |
| Programming Toolchain | Altera MAX+PLUS II | — |
| Package Type | Pin Grid Array (PGA), ceramic | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Operating Temperature | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Speed Grade | -2 | -1 |
| RoHS Status | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Mounting Type | Through-hole (PGA socket) | — |
| Device Type | — | EPLD / CPLD |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| Number of Pins | — | 84 |
| Propagation Delay | — | 25 ns |
| Maximum Clock Frequency | — | 50 MHz |
| Supply Voltage | — | 5 V nominal (4.75 V to 5.25 V) |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |