EPM5192GC-2 vs EPM5192LC-1 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GC-2 sa pamamagitan ng Altera at EPM5192LC-1 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GC-2 | EPM5192LC-1 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Macrocells | 192 | 192 |
| Logic Array Blocks | 16 (LABs of 16 macrocells each) | — |
| Usable I/O Pins | [DATA_NEEDED: exact user I/O count for PGA package] | — |
| Propagation Delay (tPD) | 12 ns typical (-2 grade) | — |
| Counter Frequency | 100 MHz minimum | — |
| Supply Voltage (VCC) | 5 V nominal | — |
| Technology | CMOS EPROM | CMOS, UV-erasable / OTP EPROM cell |
| Programmable Technology | UV-erasable / one-time programmable | — |
| Programming Toolchain | Altera MAX+PLUS II | — |
| Package Type | Pin Grid Array (PGA), ceramic | LDCC (Leaded Ceramic Chip Carrier), plastic windowless |
| Temperature na Operasyon | Commercial (0C to +70C) | 0C to +70C (commercial) |
| Speed Grade | -2 | -1 |
| Tindminan RoHS | Non-Compliant (ceramic PGA, lead-bearing per GlobalSpec listing) | Non-compliant (ceramic LDCC with Pb-bearing terminations) |
| Uri ng Pagpapasok | Through-hole (PGA socket) | — |
| Device Type | — | EPLD / CPLD |
| Logic Gates | — | 3750 (typical usable) |
| Dedicated Inputs | — | 7 |
| User I/O | — | 64 |
| Bilang ng Pins | — | 84 |
| Propagation Delay | — | 25 ns |
| Maksimum na Taktiko ng Oras | — | 50 MHz |
| Volte ng Pagbibigay | — | 5 V nominal (4.75 V to 5.25 V) |
| Programmable Memory | — | EPROM (one-time or UV-erasable) |