EPM5192GM883B vs EPM5192JC-ES Comparison
Detailed side-by-side comparison of EPM5192GM883B by Intel and EPM5192JC-ES by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192GM883B | EPM5192JC-ES |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-erasable) | CPLD (EPLD) |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Maximum Clock Frequency | 33.3 MHz | — |
| Propagation Delay (tpd) | 55 ns | — |
| Package | 84-terminal CPGA (Ceramic Pin Grid Array) | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| Package Body Size | 28.45 mm square | — |
| Process Technology | CMOS | — |
| Mounting Type | Through-Hole (PGA) | Surface Mount |
| Military Screening | MIL-STD-883 Revision B | — |
| Programming Technology | UV-EPROM (non-volatile) | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Technology | — | CMOS |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range for ES grade] |
| Supply Voltage | — | [DATA_NEEDED: VCC nominal] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| MSL Level | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |