EPM5192GM883B vs EPM5192JC-ES Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192GM883B sa pamamagitan ng Intel at EPM5192JC-ES sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM5192GM883B | EPM5192JC-ES |
|---|---|---|
| Brand | Intel | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD (UV-erasable) | CPLD (EPLD) |
| Macrocells | 192 | 192 |
| Dedicated Inputs | 7 | — |
| User I/O Pins | 64 | [DATA_NEEDED: user I/O count for JC-ES in PLCC-84] |
| Nominal Supply Voltage (VCC) | 5 V | — |
| Maksimum na Taktiko ng Oras | 33.3 MHz | — |
| Propagation Delay (tpd) | 55 ns | — |
| Packhaging | 84-terminal CPGA (Ceramic Pin Grid Array) | 84-pin PLCC (J-lead, CQCC, JEDEC S-CQCC-J84) |
| Package Body Size | 28.45 mm square | — |
| Process Technology | CMOS | — |
| Uri ng Pagpapasok | Through-Hole (PGA) | Surface Mount |
| Military Screening | MIL-STD-883 Revision B | — |
| Programming Technology | UV-EPROM (non-volatile) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Configuration Memory | — | EPROM (UV-erasable, one-time programmable for JC-ES) |
| Technology | — | CMOS |
| Programming | — | Altera MAX+PLUS II or compatible programmer |
| Temperature na Operasyon | — | [DATA_NEEDED: operating temperature range for ES grade] |
| Volte ng Pagbibigay | — | [DATA_NEEDED: VCC nominal] |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |
| Level ng MSL | — | [DATA_NEEDED: MSL rating] |
| Note | — | Datasheet source: Altera MAX 5000 family document, 52 pages |