EPM5192LC-1 vs EPM5192-1LC Comparison
Detailed side-by-side comparison of EPM5192LC-1 by Altera and EPM5192-1LC by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-1 | EPM5192-1LC |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Number of Pins | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | — |
| Maximum Clock Frequency | 50 MHz | — |
| Supply Voltage | 5 V nominal (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | — |
| RoHS Status | Non-compliant (ceramic LDCC with Pb-bearing terminations) | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Process Technology | — | UV EPROM, erasable windowless |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| Package | — | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| Mounting Type | — | Surface Mount |