EPM5192LC-1 vs EPM5192-1LC 比較
詳細な並列比較: EPM5192LC-1 メーカー: Altera および EPM5192-1LC メーカー: Altera。主要仕様、電気的特性、パッケージ、ライフサイクルステータス、価格、在庫状況を比較して、設計要件に最適な部品を判断してください。
仕様比較
| パラメータ | EPM5192LC-1 | EPM5192-1LC |
|---|---|---|
| ブランド | Altera | Altera |
| カテゴリ | FPGA & CPLD | FPGA & CPLD |
| ライフサイクル状態 | Obsolete | Obsolete |
| 在庫状況 | In Stock | In Stock |
| 単価（USD） | $14.20 | $19.40 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD / CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| ピン数 | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | — |
| 最大クロック周波数 | 50 MHz | — |
| 電源電圧 | 5 V nominal (4.75 V to 5.25 V) | 5 V |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| 動作温度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | — |
| RoHS ステータス | Non-compliant (ceramic LDCC with Pb-bearing terminations) | Non-compliant (ceramic windowless package, lead-bearing termination) |
| Usable Gates | — | 3,750 |
| Logic Array Blocks (LABs) | — | 4 |
| User I/O Pins | — | 64 |
| Maximum Operating Frequency | — | 62.5 MHz |
| Propagation Delay (tpd) | — | [DATA_NEEDED: -1 speed grade tpd in ns] |
| Process Technology | — | UV EPROM, erasable windowless |
| Programmable Interconnect | — | PIA (Programmable Interconnect Array) |
| JTAG Boundary Scan | — | IEEE 1149.1 compliant |
| パッケージ | — | 64-pin Ceramic J-Lead Chip Carrier (LC) |
| 実装タイプ | — | Surface Mount |