EPM5192LC-1 vs EPM5192JC Comparison
Detailed side-by-side comparison of EPM5192LC-1 by Altera and EPM5192JC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-1 | EPM5192JC |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Number of Pins | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | [DATA_NEEDED: tpd spec by speed grade] |
| Maximum Clock Frequency | 50 MHz | — |
| Supply Voltage | 5 V nominal (4.75 V to 5.25 V) | [DATA_NEEDED: VCC nominal] |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: commercial / industrial / military grade] |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | — |
| RoHS Status | Non-compliant (ceramic LDCC with Pb-bearing terminations) | [DATA_NEEDED: original Altera marking not RoHS] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Package | — | 68-pin PLCC (JC) windowed ceramic |
| Mounting Type | — | Surface Mount |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |