EPM5192LC-1 vs EPM5192JC Comparación
Comparación detallada lado a lado de EPM5192LC-1 por Altera y EPM5192JC por Intel. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Comparación de especificaciones
| Parámetro | EPM5192LC-1 | EPM5192JC |
|---|---|---|
| Marca | Altera | Intel |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Obsolete | Obsolete |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $14,20 | $16,40 |
| Family | MAX 5000 | — |
| Device Type | EPLD / CPLD | — |
| Macrocells | 192 | 192 |
| Logic Gates | 3750 (typical usable) | — |
| Dedicated Inputs | 7 | — |
| User I/O | 64 | — |
| Número de pines | 84 | — |
| Package Type | LDCC (Leaded Ceramic Chip Carrier), plastic windowless | — |
| Propagation Delay | 25 ns | [DATA_NEEDED: tpd spec by speed grade] |
| Frecuencia de reloj máxima | 50 MHz | — |
| Tensión de alimentación | 5 V nominal (4.75 V to 5.25 V) | [DATA_NEEDED: VCC nominal] |
| Technology | CMOS, UV-erasable / OTP EPROM cell | — |
| Temperatura de funcionamiento | 0C to +70C (commercial) | [DATA_NEEDED: commercial / industrial / military grade] |
| Programmable Memory | EPROM (one-time or UV-erasable) | — |
| Speed Grade | -1 | — |
| Estado RoHS | Non-compliant (ceramic LDCC with Pb-bearing terminations) | [DATA_NEEDED: original Altera marking not RoHS] |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Series | — | EPM5192 (Classic / MAX-class) |
| Logic Array Blocks (LABs) | — | 12 |
| Interconnect Architecture | — | Programmable Interconnect Array (PIA) |
| Process Technology | — | CMOS EPROM (UV-erasable) |
| Encapsulado | — | 68-pin PLCC (JC) windowed ceramic |
| Tipo de montaje | — | Surface Mount |
| Programming Method | — | UV-erase + EPROM programmer |
| Non-Volatile Configuration | — | Yes (EPROM cell array) |
| Logic Family | — | Classic CPLD (EPM5xxx series) |