EPM5192LC-2 vs EPM5192JC-2 Comparison
Detailed side-by-side comparison of EPM5192LC-2 by Altera and EPM5192JC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-2 | EPM5192JC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Input Pins | 7 | — |
| External Clock Inputs | 1 | 1 |
| Propagation Delay (tPD) | 45 ns (typical, -2 speed grade) | 45 ns |
| Maximum Internal Frequency | 50 MHz | — |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Process Technology | CMOS | CMOS |
| Package | PQCC-84 (PLCC-84, J-lead, surface mount) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Programming | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) | — |
| Operating Temperature | [DATA_NEEDED: commercial/industrial/military grade] | — |
| Supply Voltage | 5 V (typical MAX 5000 family) | — |
| RoHS Status | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Dedicated Inputs | — | 7 |
| Maximum Clock Frequency | — | 40 MHz |
| Mounting Type | — | Surface Mount |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |