EPM5192LC-2 vs EPM5192JC-2 比較
詳細並排比較 EPM5192LC-2 由 Altera 與 EPM5192JC-2 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM5192LC-2 | EPM5192JC-2 |
|---|---|---|
| 品牌 | Altera | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 5000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | 64 |
| Dedicated Input Pins | 7 | — |
| External Clock Inputs | 1 | 1 |
| Propagation Delay (tPD) | 45 ns (typical, -2 speed grade) | 45 ns |
| Maximum Internal Frequency | 50 MHz | — |
| Interconnect | Programmable Interconnect Array (PIA) | Programmable Interconnect Array (PIA) |
| Process Technology | CMOS | CMOS |
| 封裝 | PQCC-84 (PLCC-84, J-lead, surface mount) | 84-pin CQCC (Ceramic Quad Flat Pack, J-lead, windowed) |
| Programming | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) | — |
| 工作溫度 | [DATA_NEEDED: commercial/industrial/military grade] | — |
| 供應電壓 | 5 V (typical MAX 5000 family) | — |
| RoHS 狀態 | [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS] | [DATA_NEEDED: RoHS compliance] |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-erasable Programmable Logic Device (PLD) |
| Dedicated Inputs | — | 7 |
| 最大時脈頻率 | — | 40 MHz |
| 安裝類型 | — | Surface Mount |
| Number of Terminals | — | 84 |
| Programming Method | — | UV-erase / EPROM |
| 工作溫度範圍 | — | [DATA_NEEDED: operating temperature range] |