EPM5192LC-35 vs EPM5192LC-2 Comparison

Detailed side-by-side comparison of EPM5192LC-35 by Altera and EPM5192LC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-35 EPM5192LC-2
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Series MAX 5000 —
Family MAX 5000 CPLD MAX 5000
Logic Elements / Macrocells 192 macrocells —
Pin-to-Pin Delay (tPD) 35 ns —
Speed Grade -35 —
Programmable Type UV-Erasable / OTP (EPROM-based) —
Package Type JLCC (J-Lead Ceramic Chip Carrier) —
Mounting Type Surface Mount —
Logic Voltage 5 V TTL-compatible I/O —
Operating Temperature Commercial (0C to +70C) per LC suffix [DATA_NEEDED: commercial/industrial/military grade]
Programming Method Altera legacy programmer (EPROM-based) —
Architecture LAB-based with Programmable Interconnect Array (PIA) —
I/O Standard TTL —
RoHS Status Non-compliant (ceramic hermetic package) [DATA_NEEDED: pre-RoHS legacy part — likely non-RoHS]
Lifecycle Status Obsolete - last-time-buy stock only —
Datasheet Document Altera MAX 5000 family datasheet (per alldatasheet.com) —
Device Type — CPLD (Complex Programmable Logic Device)
Macrocells — 192
Logic Array Blocks (LABs) — 12
User I/O Pins — 64
Dedicated Input Pins — 7
External Clock Inputs — 1
Propagation Delay (tPD) — 45 ns (typical, -2 speed grade)
Maximum Internal Frequency — 50 MHz
Interconnect — Programmable Interconnect Array (PIA)
Process Technology — CMOS
Package — PQCC-84 (PLCC-84, J-lead, surface mount)
Programming — Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG)
Supply Voltage — 5 V (typical MAX 5000 family)

Datasheets & Resources

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