EPM5192LC-35 vs EPM5192LC-25 Comparison
Detailed side-by-side comparison of EPM5192LC-35 by Altera and EPM5192LC-25 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC-35 | EPM5192LC-25 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | MAX 5000 | — |
| Family | MAX 5000 CPLD | MAX 5000 |
| Logic Elements / Macrocells | 192 macrocells | — |
| Pin-to-Pin Delay (tPD) | 35 ns | 25 ns |
| Speed Grade | -35 | -25 (25 ns) |
| Programmable Type | UV-Erasable / OTP (EPROM-based) | — |
| Package Type | JLCC (J-Lead Ceramic Chip Carrier) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Logic Voltage | 5 V TTL-compatible I/O | — |
| Operating Temperature | Commercial (0C to +70C) per LC suffix | 0C to +70C (commercial) |
| Programming Method | Altera legacy programmer (EPROM-based) | — |
| Architecture | LAB-based with Programmable Interconnect Array (PIA) | — |
| I/O Standard | TTL | TTL-compatible |
| RoHS Status | Non-compliant (ceramic hermetic package) | Unknown (legacy ceramic package typically non-RoHS) |
| Lifecycle Status | Obsolete - last-time-buy stock only | — |
| Datasheet Document | Altera MAX 5000 family datasheet (per alldatasheet.com) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Logic Elements | — | 192 (1 macrocell ≈ 1 LE in MAX 5000 architecture) |
| Package | — | JLCC-84 (ceramic J-lead chip carrier) |
| Programmable Technology | — | UV-erasable / OTP (EPROM-based) |
| Programming Interface | — | JTAG / Altera programming hardware (legacy) |
| Supply Voltage | — | 5 V (typical, MAX 5000) |
| Configuration Memory | — | Non-volatile EPROM (on-chip) |
| Manufacturer | — | Altera Corporation (now Intel PSG) |