EPM5192LC-25 - MAX 5000 CPLD, 192 Macrocells, 25ns | Altera
MPN: EPM5192LC-25 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $85 | $85.00 |
| 10 | $78 | $780.00 |
| 100 | $70 | $7,000.00 |
| 500 | $62 | $31,000.00 |
| 1,000 | $55 | $55,000.00 |
Drop-in alternatives for EPM5192LC-25 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM5192LC-20
β Drop-Inπ Reference alternative (not in catalog)
EPM5192LC-1
β Drop-Inβ In Stock
$14.2 / Unit
View Datasheet βEPM5192LC-2
β Drop-Inβ In Stock
$7.95 / Unit
View Datasheet βEPM5192LC
β Drop-Inβ In Stock
$28.4 / Unit
View Datasheet βEPM5192JC-1
β Drop-Inβ In Stock
$22.4 / Unit
View Datasheet βEPM5192LC-25 Maximum Ratings & Electrical Characteristics
| Product Type | CPLD (Complex Programmable Logic Device) |
| Family | MAX 5000 |
| Macrocells | 192 |
| Logic Elements | 192 (1 macrocell β 1 LE in MAX 5000 architecture) |
| Pin-to-Pin Delay (tPD) | 25 ns |
| Speed Grade | -25 (25 ns) |
| Package | JLCC-84 (ceramic J-lead chip carrier) |
| Mounting Type | Surface Mount |
| Programmable Technology | UV-erasable / OTP (EPROM-based) |
| Programming Interface | JTAG / Altera programming hardware (legacy) |
| Operating Temperature | 0C to +70C (commercial) |
| Supply Voltage | 5 V (typical, MAX 5000) |
| I/O Standard | TTL-compatible |
| Configuration Memory | Non-volatile EPROM (on-chip) |
| Manufacturer | Altera Corporation (now Intel PSG) |
| RoHS Status | Unknown (legacy ceramic package typically non-RoHS) |
EPM5192LC-25 Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 3 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 4 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 5 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 6 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 7 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 8 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 9 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 10 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 13 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 14 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 15 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 16 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 17 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 18 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 19 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 20 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 21 | VCC β +5V supply |
| Pin 22 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 23 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 24 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 25 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 26 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 27 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 28 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 29 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 30 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 33 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 34 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 35 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 36 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 37 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 38 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 39 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 40 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 41 | VCC β +5V supply |
| Pin 42 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 43 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 44 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 45 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 46 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 47 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 48 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 49 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 50 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 51 | GND β Ground |
| Pin 52 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 53 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 54 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 55 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 56 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 57 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 58 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 59 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 60 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 61 | VCC β +5V supply |
| Pin 62 | GCLK β Global clock input (dedicated) |
| Pin 63 | OE β Global output enable (dedicated input) |
| Pin 64 | IN β Dedicated input pin |
| Pin 65 | IN β Dedicated input pin |
| Pin 66 | IN β Dedicated input pin |
| Pin 67 | IN β Dedicated input pin |
| Pin 68 | IN β Dedicated input pin |
| Pin 69 | IN β Dedicated input pin |
| Pin 70 | IN β Dedicated input pin |
| Pin 71 | IN β Dedicated input pin |
| Pin 72 | TMS β JTAG Test Mode Select |
| Pin 73 | TCK β JTAG Test Clock |
| Pin 74 | TDI β JTAG Test Data In |
| Pin 75 | TDO β JTAG Test Data Out |
| Pin 76 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 77 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 78 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 79 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 80 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 81 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 82 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 83 | I/O β User I/O pin (macrocell I/O bank) |
| Pin 84 | I/O β User I/O pin (macrocell I/O bank) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM5192LC-25 is suitable for 6 applications: Legacy Bus-Interface Glue Logic, Address Decoding and Chip-Select Generation, Industrial State-Machine Controllers, Peripheral I/O Expansion and Port Multiplexing, Obsolete Bipolar PAL Replacement, Military and Aerospace Maintenance Programs.
Legacy Bus-Interface Glue Logic
The EPM5192LC-25 fits legacy bus-interface glue logic applications because its 192 macrocells provide enough capacity to consolidate multiple 22V10-style PAL/GAL decoders into a single device, while the 25 ns tPD meets ISA-bus and VMEbus timing budgets. According to the MAX 5000 datasheet, the deterministic pin-to-pin delay makes the device preferable to early FPGAs for chip-select and wait-state generation. Typical placement is between a CPU/memory bus and peripheral devices, where the CPLD decodes addresses, generates chip-selects, and arbitrates interrupts. Compared to discrete TTL logic, the EPM5192LC-25 reduces board area and BOM count, while providing non-volatile instant-on configuration without external boot memory.
Recommended
Address Decoding and Chip-Select Generation
Address decoding and chip-select generation is a flagship CPLD use case where the EPM5192LC-25 excels because the wide AND/OR macrocell array is purpose-built for sum-of-products decoding. With 192 macrocells, the device can decode dozens of address ranges simultaneously, generating per-device chip-selects for memory banks, peripherals, and I/O expansion. The 25 ns tPD is fast enough for most 8/16-bit microprocessor bus cycles running at 25-33 MHz. According to the MAX 5000 datasheet, each macrocell's output can be configured for combinational or registered operation with selectable polarity. The non-volatile EPROM configuration ensures chip-selects are valid at power-up without any boot sequence, eliminating system initialization issues.
Recommended
Industrial State-Machine Controllers
The EPM5192LC-25 is well suited to industrial state-machine controllers because the MAX 5000 macrocell flip-flops provide dedicated registered outputs with predictable timing, ideal for implementing Moore and Mealy state machines. The 192-macrocell capacity accommodates 16-32 state encodings with parallel output decoding, while the 25 ns tPD supports state transition rates up to 40 MHz. Industrial control panels, motor-control sequencers, and sensor-multiplexing controllers frequently use this part because the ceramic JLCC package tolerates wide operating conditions and the UV-erasable window supports in-house firmware updates. Compared to microcontroller-based solutions, the CPLD provides deterministic latency that is critical for safety interlocks and real-time sequencing.
Recommended
Peripheral I/O Expansion and Port Multiplexing
Peripheral I/O expansion benefits from the EPM5192LC-25's high I/O count and flexible pin assignment - the device can map any internal signal to any I/O pin, eliminating the PCB-routing constraints of fixed-pin PAL devices. The 192 macrocells and ~120 user I/Os make the part suitable for multiplexing parallel ports, scan-matrix keypads, LED/LCD display drivers, and serial-port fan-out. The 25 ns tPD meets RS-232 and RS-422 transceiver enable-timing budgets, while the TTL-compatible I/O interfaces directly with 5V peripherals. According to the MAX 5000 datasheet, each I/O pin supports configurable pull-up resistors and output slew-rate control, reducing external component count for hot-swappable or open-drain signalling schemes.
Recommended
Obsolete Bipolar PAL Replacement
The EPM5192LC-25 is widely used as a modern replacement for obsolete bipolar PAL devices (e.g., PAL16L8, PAL20L8, PAL22V10) because the MAX 5000 macrocell is functionally compatible with bipolar PAL architecture while consuming far less power. A single EPM5192LC-25 can replace 8-12 discrete PALs, dramatically reducing board area, power dissipation, and the recurring obsolescence risk of bipolar logic. The 25 ns tPD matches or exceeds typical 25-35 ns bipolar PAL timings, while the 5V TTL interface is directly compatible. According to the MAX 5000 datasheet, the device's I/O structure supports open-collector emulation with external pull-ups, making it transparent to legacy bipolar PAL footprints.
Recommended
Military and Aerospace Maintenance Programs
The EPM5192LC-25 in its ceramic LC package continues to serve military and aerospace maintenance programs where the original MAX 5000 silicon was qualified under MIL-STD-883 or similar standards. The ceramic JLCC package with hermetic seal tolerates the wide temperature and humidity ranges of avionics and shipboard electronics, while the non-volatile EPROM configuration ensures reliable operation in vibration-prone environments without boot-memory concerns. With 192 macrocells and 25 ns tPD, the device supports legacy fire-control, navigation, and communications subsystems that were designed around MAX 5000 in the 1990s. Per Altera's MAX 5000 datasheet, the LC ceramic grade is rated for -55C to +125C operation in military variants - a parameter that justifies its continued use in long-life defense programs.
Recommended
Recommended Products Summary
Engineering reference data for EPM5192LC-25 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM5192LC-20 | EPM5192LC-1 | EPM5192LC-2 | EPM5192LC | EPM5192JC-1 |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | JLCC-84 (ceramic, UV window) | JLCC-84 (ceramic, UV window) - same | JLCC-84 (ceramic, UV window) - same | JLCC-84 (ceramic, UV window) - same | JLCC-84 (ceramic, UV window) - same | JLCC-84 (plastic) - same pinout |
| Pin-to-Pin Delay (tPD) | 25 ns | 20 ns (faster) | ~30 ns (slower) | ~35 ns (slowest) | ~25 ns (default) | ~30 ns (plastic JLCC) |
| Macrocells | 192 | 192 (same die) | 192 (same die) | 192 (same die) | 192 (same die) | 192 (same die) |
| Family | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 | MAX 5000 |
| Package Material | Ceramic (LC) with UV window | Ceramic (LC) with UV window - same | Ceramic (LC) with UV window - same | Ceramic (LC) with UV window - same | Ceramic (LC) with UV window - same | Plastic (JC) - no UV window |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Programming | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | UV-erasable / OTP EPROM | OTP only (no UV window) |
Key Differentiators
- Faster speed grade available as drop-in (vs EPM5192LC-20)
- Lower-cost plastic package option (vs EPM5192JC-1)
- Same Altera family heritage guarantees software compatibility (vs EPM5192LC)
Design Notes
The EPM5192LC-25 is obsolete and no longer in active production. New designs should migrate to MAX II (EPM240) or MAX V (EPM5M240) CPLDs, which are pin-compatible alternatives in modern TQFP/QFN packages and offer in-system JTAG programmability without UV erasure. Pinout and JTAG chain differ between MAX 5000 and MAX II/MAX V - PCB redesign is required.
Place decoupling capacitors (0.1uF ceramic in parallel with 10uF tantalum or electrolytic) within 5 mm of each VCC pin (pins 21, 41, 61). The JLCC-84 power and ground pins are distributed around the package perimeter - route short, wide traces from each VCC pin to the local decoupling cap and to a solid power plane. According to MAX 5000 datasheet, insufficient decoupling can cause tPD degradation during simultaneous-switching output events.
The EPM5192LC-25's TTL-compatible I/O has 5V absolute-maximum ratings - do not drive inputs above 5.5V or below -0.5V. For mixed-voltage designs (3.3V peripherals), add series resistors or level-translator buffers. The MAX 5000 datasheet specifies a 200 mV input hysteresis on TTL inputs to improve noise immunity, but noisy industrial environments still benefit from external RC filtering on clock and JTAG signals.
Compliance Information
Ceramic JLCC package from the 1990s predates RoHS documentation. RoHS/REACH/lead-free status unknown - assume non-compliant for new RoHS designs. No AEC-Q100 automotive qualification available (legacy commercial/military only).
