EPM5192LC-M091A vs EPM5192LC-35 Comparison

Detailed side-by-side comparison of EPM5192LC-M091A by Altera and EPM5192LC-35 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM5192LC-M091A EPM5192LC-35
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Device Family MAX 5000 EPLD —
Macrocells 192 —
User I/O Pins 64 —
Dedicated Inputs 7 —
Logic Array Blocks (LABs) 12 —
Global Clock Inputs 1 —
Propagation Delay (tpd) 55 ns (typical, MAX 5000 family) —
Supply Voltage (Vcc) 5 V —
Technology UV-erasable CMOS, EPROM-based —
Interconnect Programmable Interconnect Array (PIA) —
Package LC (custom pin-grid / customer-specific, M091A designation) —
Pin Count [DATA_NEEDED: pin count of LC-M091A package] —
Operating Temperature [DATA_NEEDED: operating temperature grade] Commercial (0C to +70C) per LC suffix
Configuration Memory Non-volatile EPROM (UV-erasable) —
Development Tool Altera MAX+PLUS II (legacy) —
RoHS Status [DATA_NEEDED: RoHS status for EPM5192LC-M091A] Non-compliant (ceramic hermetic package)
Series — MAX 5000
Family — MAX 5000 CPLD
Logic Elements / Macrocells — 192 macrocells
Pin-to-Pin Delay (tPD) — 35 ns
Speed Grade — -35
Programmable Type — UV-Erasable / OTP (EPROM-based)
Package Type — JLCC (J-Lead Ceramic Chip Carrier)
Mounting Type — Surface Mount
Logic Voltage — 5 V TTL-compatible I/O
Programming Method — Altera legacy programmer (EPROM-based)
Architecture — LAB-based with Programmable Interconnect Array (PIA)
I/O Standard — TTL
Lifecycle Status — Obsolete - last-time-buy stock only
Datasheet Document — Altera MAX 5000 family datasheet (per alldatasheet.com)

Datasheets & Resources

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