EPM5192LC-M091A vs EPM5192LC-35 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM5192LC-M091A sa pamamagitan ng Altera at EPM5192LC-35 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM5192LC-M091A EPM5192LC-35
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Device Family MAX 5000 EPLD —
Macrocells 192 —
User I/O Pins 64 —
Dedicated Inputs 7 —
Logic Array Blocks (LABs) 12 —
Global Clock Inputs 1 —
Propagation Delay (tpd) 55 ns (typical, MAX 5000 family) —
Supply Voltage (Vcc) 5 V —
Technology UV-erasable CMOS, EPROM-based —
Interconnect Programmable Interconnect Array (PIA) —
Packhaging LC (custom pin-grid / customer-specific, M091A designation) —
Bilang ng Pin [DATA_NEEDED: pin count of LC-M091A package] —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] Commercial (0C to +70C) per LC suffix
Configuration Memory Non-volatile EPROM (UV-erasable) —
Development Tool Altera MAX+PLUS II (legacy) —
Tindminan RoHS [DATA_NEEDED: RoHS status for EPM5192LC-M091A] Non-compliant (ceramic hermetic package)
Series — MAX 5000
Family — MAX 5000 CPLD
Logic Elements / Macrocells — 192 macrocells
Pin-to-Pin Delay (tPD) — 35 ns
Speed Grade — -35
Programmable Type — UV-Erasable / OTP (EPROM-based)
Package Type — JLCC (J-Lead Ceramic Chip Carrier)
Uri ng Pagpapasok — Surface Mount
Logic Voltage — 5 V TTL-compatible I/O
Programming Method — Altera legacy programmer (EPROM-based)
Architecture — LAB-based with Programmable Interconnect Array (PIA)
I/O Standard — TTL
Katayuan ng Lifecycle — Obsolete - last-time-buy stock only
Datasheet Document — Altera MAX 5000 family datasheet (per alldatasheet.com)

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