EPM5192LC vs EPM5192JC Comparison
Detailed side-by-side comparison of EPM5192LC by Altera and EPM5192JC by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC | EPM5192JC |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $28.40 | $16.40 |
| Family | MAX 7000S | β |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 12 |
| User I/O Pins | 64 | β |
| Dedicated Inputs | 7 | β |
| Global Clock Inputs | 1 | β |
| Propagation Delay (tPD) | 55 ns (typical, commercial) | β |
| Maximum Clock Frequency (fMAX) | 50 MHz | β |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (nominal 5 V) | β |
| Process Technology | CMOS, UV-erasable/OTP EPROM configuration | CMOS EPROM (UV-erasable) |
| Programmable Interconnect | Programmable Interconnect Array (PIA), fixed delay | β |
| Boundary-Scan Support | JTAG IEEE 1149.1 | β |
| Programming Interface | JTAG (ByteBlaster-compatible) | β |
| Operating Temperature (commercial) | 0C to +70C | β |
| Package | JLCC-68 (windowed ceramic, LC suffix) | 68-pin PLCC (JC) windowed ceramic |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: original Altera marking not RoHS] |
| Product Type | β | CPLD (Complex Programmable Logic Device) |
| Series | β | EPM5192 (Classic / MAX-class) |
| Interconnect Architecture | β | Programmable Interconnect Array (PIA) |
| Programming Method | β | UV-erase + EPROM programmer |
| Non-Volatile Configuration | β | Yes (EPROM cell array) |
| Logic Family | β | Classic CPLD (EPM5xxx series) |
| Operating Temperature | β | [DATA_NEEDED: commercial / industrial / military grade] |
| Supply Voltage | β | [DATA_NEEDED: VCC nominal] |
| Propagation Delay | β | [DATA_NEEDED: tpd spec by speed grade] |