EPM5192LC1 vs EPM5192LC-2 Comparison
Detailed side-by-side comparison of EPM5192LC1 by Altera and EPM5192LC-2 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LC1 | EPM5192LC-2 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $17.40 | $7.95 |
| Family | MAX 5000 | MAX 5000 |
| Device Type | Complex PLD (CPLD), UV-erasable/OTP | CPLD (Complex Programmable Logic Device) |
| Macrocells | 192 | 192 |
| Equivalent Gates | 3750 | β |
| Dedicated Inputs | 7 | β |
| User I/O Pins | 64 | 64 |
| Package | PQCC-84 (JEDEC S-PQCC-J84, 84-lead Plastic Leaded Chip Carrier) | PQCC-84 (PLCC-84, J-lead, surface mount) |
| Nominal Supply Voltage (VCC) | 5 V | β |
| Supply Voltage Range | 4.75 V to 5.25 V | β |
| Maximum Clock Frequency | 50 MHz | β |
| Propagation Delay (tPD) | 40 ns | 45 ns (typical, -2 speed grade) |
| Process Technology | CMOS EPROM | CMOS |
| Programming Method | OTP (LC plastic package); UV-erasable equivalents in JC ceramic package | β |
| Operating Temperature (Commercial 'LC') | 0 Β°C to 70 Β°C | β |
| Mounting Type | Surface Mount | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: pre-RoHS legacy part β likely non-RoHS] |
| JEDEC Package Code | S-PQCC-J84 | β |
| Logic Array Blocks (LABs) | β | 12 |
| Dedicated Input Pins | β | 7 |
| External Clock Inputs | β | 1 |
| Maximum Internal Frequency | β | 50 MHz |
| Interconnect | β | Programmable Interconnect Array (PIA) |
| Programming | β | Non-volatile (EPROM/EEPROM-based, in-system programmable via JTAG) |
| Operating Temperature | β | [DATA_NEEDED: commercial/industrial/military grade] |
| Supply Voltage | β | 5 V (typical MAX 5000 family) |