EPM5192LI-2 vs EPM5192LI84 Comparison
Detailed side-by-side comparison of EPM5192LI-2 by Altera and EPM5192LI84 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM5192LI-2 | EPM5192LI84 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $7.90 | $21.60 |
| Family | MAX 5000 | β |
| Device Type | EPLD (Erasable/OTP Complex PLD) | β |
| Macrocells | 192 | β |
| Logic Array Blocks (LABs) | 12 | β |
| User I/O | 64 | β |
| Total Inputs | 72 (7 dedicated + 64 I/O) | β |
| Propagation Delay (tpd) | 55 ns (max) | β |
| Maximum Internal Frequency | 100 MHz | β |
| Supply Voltage | 4.5 V to 5.5 V | β |
| Operating Temperature | -40 C to +85 C (industrial) | β |
| Typical Power Dissipation | 600 mW at 5 V / 25 C | β |
| Technology | CMOS, UV-erasable / OTP | β |
| Package | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 | β |
| Mounting Type | Surface Mount | Surface Mount (socket-compatible) |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Design Toolchain | Altera MAX+plus II | β |
| Device Family | β | MAX 5000 |
| Product Type | β | UV-Erasable/OTP Complex PLD (CPLD) |
| Usable Gates | β | 3,750 gates |
| Macro Cells | β | 192 |
| Maximum Toggle Frequency | β | 40 MHz |
| Pin-to-Pin Delay (tPD) | β | 25 ns |
| Supply Voltage (VCC) | β | 5 V (single supply) |
| User I/O Pins | β | 64 (max) |
| Operating Temperature Range | β | -40 Β°C to +85 Β°C (industrial) |
| Package Type | β | 84-pin PLCC (J-lead, package code J84/QCCJ) |
| Configuration Memory | β | OTP / UV-erasable EPROM |
| Programming Method | β | Stand-alone programmer (no JTAG on LI84 OTP variant) |
| Logic Compatibility | β | TTL-compatible I/O |