EPM5192LI-2 vs EPM5192LI84 Vergleich
Detaillierter Direktvergleich von EPM5192LI-2 von Altera und EPM5192LI84 von Altera. Vergleichen Sie die wichtigsten Spezifikationen, elektrischen Parameter, Gehäuse, Lebenszyklusstatus, Preise und Verfügbarkeit, um das beste Bauteil für Ihre Designanforderungen zu ermitteln.
Spezifikationsvergleich
| Parameter | EPM5192LI-2 | EPM5192LI84 |
|---|---|---|
| Marke | Altera | Altera |
| Kategorie | FPGA & CPLD | FPGA & CPLD |
| Lebenszyklusstatus | Obsolete | Obsolete |
| Lagerstatus | In Stock | In Stock |
| Stückpreis (USD) | $7,90 | $21,60 |
| Family | MAX 5000 | — |
| Device Type | EPLD (Erasable/OTP Complex PLD) | — |
| Macrocells | 192 | — |
| Logic Array Blocks (LABs) | 12 | — |
| User I/O | 64 | — |
| Total Inputs | 72 (7 dedicated + 64 I/O) | — |
| Propagation Delay (tpd) | 55 ns (max) | — |
| Maximum Internal Frequency | 100 MHz | — |
| Versorgungsspannung | 4.5 V to 5.5 V | — |
| Betriebstemperatur | -40 C to +85 C (industrial) | — |
| Typical Power Dissipation | 600 mW at 5 V / 25 C | — |
| Technology | CMOS, UV-erasable / OTP | — |
| Gehäuse | 84-pin PLCC (J-lead), JEDEC S-PQCC-J84 | — |
| Montageart | Surface Mount | Surface Mount (socket-compatible) |
| RoHS-Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Design Toolchain | Altera MAX+plus II | — |
| Device Family | — | MAX 5000 |
| Product Type | — | UV-Erasable/OTP Complex PLD (CPLD) |
| Usable Gates | — | 3,750 gates |
| Macro Cells | — | 192 |
| Maximum Toggle Frequency | — | 40 MHz |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Supply Voltage (VCC) | — | 5 V (single supply) |
| User I/O Pins | — | 64 (max) |
| Betriebstemperaturbereich | — | -40 °C to +85 °C (industrial) |
| Package Type | — | 84-pin PLCC (J-lead, package code J84/QCCJ) |
| Configuration Memory | — | OTP / UV-erasable EPROM |
| Programming Method | — | Stand-alone programmer (no JTAG on LI84 OTP variant) |
| Logic Compatibility | — | TTL-compatible I/O |