EPM570F100C5N vs EPM570F100I5N Comparison
Detailed side-by-side comparison of EPM570F100C5N by Altera and EPM570F100I5N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM570F100C5N | EPM570F100I5N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Family | MAX II | MAX II |
| Logic Elements | 570 | — |
| Number of Macrocells | 440 | — |
| User I/Os | 76 | — |
| Number of Logic Array Blocks | 57 | — |
| Propagation Delay (tPD) | 5.4 ns | 8.7 ns (max), 5.4 ns (typical) |
| Process Technology | 0.18 micron CMOS | CMOS, Flash configuration cell |
| Supply Voltage - Internal | 2.5 V, 3.3 V | — |
| I/O Standards Supported | 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL | LVCMOS, LVTTL, LVDS, SSTL, HSTL (1.5/1.8/2.5/3.3 V) |
| Operating Temperature | 0C to 85C (TJ) | -40C to +100C (Industrial) |
| Mounting Type | Surface Mount | Surface Mount |
| Package / Case | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch | — |
| Supplier Device Package | 100-FBGA | — |
| Configuration Memory | On-chip Flash (instant-on, non-volatile) | — |
| In-System Programmability | Yes (JTAG, IEEE 1532) | — |
| User Flash Memory (UFM) | 8 Kbit | — |
| Lead Free / RoHS | Yes (per verified data) | — |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1), in-system programmable |
| Device Type | — | CPLD (Flash-based) |
| Logic Elements (LEs) | — | 570 |
| Macrocells | — | 440 |
| Maximum User I/Os | — | 76 |
| User Flash Memory | — | 8 Kbits |
| Maximum Operating Frequency | — | 304 MHz |
| Supply Voltage (VCCINT) | — | 2.375 V to 3.6 V |
| Typical Supply Current (ICC) | — | 55 mA |
| Global Clocks | — | 4 |
| Package | — | 100-ball FineLine BGA (11x11 mm) |
| Hot Socketing | — | Supported |
| RoHS Status | — | Compliant |