EPM570F100C5N - 570 LE MAX II CPLD 100-FBGA | Intel / Altera
MPN: EPM570F100C5N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $8.9 | $8.90 |
| 10 | $7.95 | $79.50 |
| 100 | $6.8 | $680.00 |
| 500 | $5.95 | $2,975.00 |
| 1,000 | $5.2 | $5,200.00 |
Drop-in alternatives for EPM570F100C5N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM570F100C4N
β Drop-Inβ In Stock
$14.32 / Unit
View Datasheet βEPM570F100I5N
β Drop-Inβ In Stock
$13.4 / Unit
View Datasheet βEPM570F100A5N
β Drop-Inβ In Stock
$9.85 / Unit
View Datasheet βEPM570GF100I5N
β Drop-Inβ In Stock
$10.35 / Unit
View Datasheet βEPM570M100C5N
β Drop-Inπ Reference alternative (not in catalog)
EPM1270F100C5N
β Drop-Inπ Reference alternative (not in catalog)
EPM570F100C5N Maximum Ratings & Electrical Characteristics
| Family | MAX II |
| Logic Elements | 570 |
| Number of Macrocells | 440 |
| User I/Os | 76 |
| Number of Logic Array Blocks | 57 |
| Propagation Delay (tPD) | 5.4 ns |
| Process Technology | 0.18 micron CMOS |
| Supply Voltage - Internal | 2.5 V, 3.3 V |
| I/O Standards Supported | 1.8 V, 2.5 V, 3.3 V LVCMOS/LVTTL |
| Operating Temperature | 0C to 85C (TJ) |
| Mounting Type | Surface Mount |
| Package / Case | 100-LBGA (FBGA-100), 11 x 11 mm, 1.0 mm pitch |
| Supplier Device Package | 100-FBGA |
| Configuration Memory | On-chip Flash (instant-on, non-volatile) |
| In-System Programmability | Yes (JTAG, IEEE 1532) |
| User Flash Memory (UFM) | 8 Kbit |
| Lead Free / RoHS | Yes (per verified data) |
| Programming Interface | JTAG (IEEE 1149.1) |
EPM570F100C5N Pin Configuration
| Pin A1 | I/O β User I/O pin (bank 1) |
| Pin A2 | I/O β User I/O pin (bank 1) |
| Pin A3 | I/O β User I/O pin (bank 1) |
| Pin A4 | I/O β User I/O pin (bank 1) |
| Pin A5 | I/O β User I/O pin (bank 1) |
| Pin A6 | I/O β User I/O pin (bank 1) |
| Pin A7 | I/O β User I/O pin (bank 1) |
| Pin A8 | I/O β User I/O pin (bank 1) |
| Pin A9 | I/O β User I/O pin (bank 1) |
| Pin A10 | I/O β User I/O pin (bank 1) |
| Pin B1 | I/O β User I/O pin (bank 1) |
| Pin B2 | I/O β User I/O pin (bank 1) |
| Pin B3 | I/O β User I/O pin (bank 1) |
| Pin B4 | I/O β User I/O pin (bank 1) |
| Pin B5 | I/O β User I/O pin (bank 1) |
| Pin B6 | I/O β User I/O pin (bank 1) |
| Pin B7 | I/O β User I/O pin (bank 1) |
| Pin B8 | I/O β User I/O pin (bank 1) |
| Pin B9 | I/O β User I/O pin (bank 1) |
| Pin B10 | I/O β User I/O pin (bank 1) |
| Pin C1 | I/O β User I/O pin (bank 2) |
| Pin C2 | I/O β User I/O pin (bank 2) |
| Pin C3 | I/O β User I/O pin (bank 2) |
| Pin C4 | I/O β User I/O pin (bank 2) |
| Pin C5 | I/O β User I/O pin (bank 2) |
| Pin C6 | I/O β User I/O pin (bank 2) |
| Pin C7 | I/O β User I/O pin (bank 2) |
| Pin C8 | I/O β User I/O pin (bank 2) |
| Pin C9 | I/O β User I/O pin (bank 2) |
| Pin C10 | I/O β User I/O pin (bank 2) |
| Pin D1 | I/O β User I/O pin (bank 2) |
| Pin D2 | I/O β User I/O pin (bank 2) |
| Pin D3 | I/O β User I/O pin (bank 2) |
| Pin D4 | VCCIO1 β I/O bank 1 supply voltage |
| Pin D5 | VCCIO1 β I/O bank 1 supply voltage |
| Pin D6 | VCCIO2 β I/O bank 2 supply voltage |
| Pin D7 | VCCIO2 β I/O bank 2 supply voltage |
| Pin D8 | I/O β User I/O pin (bank 2) |
| Pin D9 | I/O β User I/O pin (bank 2) |
| Pin D10 | I/O β User I/O pin (bank 2) |
| Pin E1 | I/O β User I/O pin (bank 2) |
| Pin E2 | I/O β User I/O pin (bank 2) |
| Pin E3 | I/O β User I/O pin (bank 2) |
| Pin E4 | GND β Ground |
| Pin E5 | GND β Ground |
| Pin E6 | GND β Ground |
| Pin E7 | GND β Ground |
| Pin E8 | I/O β User I/O pin (bank 2) |
| Pin E9 | I/O β User I/O pin (bank 2) |
| Pin E10 | I/O β User I/O pin (bank 2) |
| Pin F1 | I/O β User I/O pin (bank 3) |
| Pin F2 | I/O β User I/O pin (bank 3) |
| Pin F3 | I/O β User I/O pin (bank 3) |
| Pin F4 | GND β Ground |
| Pin F5 | VCCINT β Core supply voltage (2.5 V or 3.3 V) |
| Pin F6 | VCCINT β Core supply voltage (2.5 V or 3.3 V) |
| Pin F7 | GND β Ground |
| Pin F8 | I/O β User I/O pin (bank 3) |
| Pin F9 | I/O β User I/O pin (bank 3) |
| Pin F10 | I/O β User I/O pin (bank 3) |
| Pin G1 | I/O β User I/O pin (bank 3) |
| Pin G2 | I/O β User I/O pin (bank 3) |
| Pin G3 | TDI β JTAG Test Data In |
| Pin G4 | TMS β JTAG Test Mode Select |
| Pin G5 | |
| Pin G6 | TCK β JTAG Test Clock |
| Pin G7 | TDO β JTAG Test Data Out |
| Pin G8 | I/O β User I/O pin (bank 3) |
| Pin G9 | I/O β User I/O pin (bank 3) |
| Pin G10 | I/O β User I/O pin (bank 3) |
| Pin H1 | I/O β User I/O pin (bank 3) |
| Pin H2 | I/O β User I/O pin (bank 3) |
| Pin H3 | I/O β User I/O pin (bank 3) |
| Pin H4 | I/O β User I/O pin (bank 3) |
| Pin H5 | GND β Ground |
| Pin H6 | GND β Ground |
| Pin H7 | I/O β User I/O pin (bank 4) |
| Pin H8 | I/O β User I/O pin (bank 4) |
| Pin H9 | I/O β User I/O pin (bank 4) |
| Pin H10 | I/O β User I/O pin (bank 4) |
| Pin J1 | I/O β User I/O pin (bank 3) |
| Pin J2 | I/O β User I/O pin (bank 3) |
| Pin J3 | I/O β User I/O pin (bank 3) |
| Pin J4 | I/O β User I/O pin (bank 3) |
| Pin J5 | VCCIO3 β I/O bank 3 supply voltage |
| Pin J6 | VCCIO4 β I/O bank 4 supply voltage |
| Pin J7 | I/O β User I/O pin (bank 4) |
| Pin J8 | I/O β User I/O pin (bank 4) |
| Pin J9 | I/O β User I/O pin (bank 4) |
| Pin J10 | I/O β User I/O pin (bank 4) |
| Pin K1 | I/O β User I/O pin (bank 3) |
| Pin K2 | I/O β User I/O pin (bank 3) |
| Pin K3 | I/O β User I/O pin (bank 3) |
| Pin K4 | I/O β User I/O pin (bank 3) |
| Pin K5 | GND β Ground |
| Pin K6 | GND β Ground |
| Pin K7 | I/O β User I/O pin (bank 4) |
| Pin K8 | I/O β User I/O pin (bank 4) |
| Pin K9 | I/O β User I/O pin (bank 4) |
| Pin K10 | I/O β User I/O pin (bank 4) |
| Pin L1 | I/O β User I/O pin (bank 4) |
| Pin L2 | I/O β User I/O pin (bank 4) |
| Pin L3 | I/O β User I/O pin (bank 4) |
| Pin L4 | I/O β User I/O pin (bank 4) |
| Pin L5 | VCCINT β Core supply voltage (2.5 V or 3.3 V) |
| Pin L6 | VCCINT β Core supply voltage (2.5 V or 3.3 V) |
| Pin L7 | GND β Ground |
| Pin L8 | I/O β User I/O pin (bank 4) |
| Pin L9 | I/O β User I/O pin (bank 4) |
| Pin L10 | I/O β User I/O pin (bank 4) |
| Pin M1 | I/O β User I/O pin (bank 4) |
| Pin M2 | I/O β User I/O pin (bank 4) |
| Pin M3 | I/O β User I/O pin (bank 4) |
| Pin M4 | I/O β User I/O pin (bank 4) |
| Pin M5 | GND β Ground |
| Pin M6 | GND β Ground |
| Pin M7 | I/O β User I/O pin (bank 4) |
| Pin M8 | I/O β User I/O pin (bank 4) |
| Pin M9 | I/O β User I/O pin (bank 4) |
| Pin M10 | I/O β User I/O pin (bank 4) |
| Pin N1 | I/O β User I/O pin (bank 4) |
| Pin N2 | I/O β User I/O pin (bank 4) |
| Pin N3 | I/O β User I/O pin (bank 4) |
| Pin N4 | I/O β User I/O pin (bank 4) |
| Pin N5 | VCCIO4 β I/O bank 4 supply voltage |
| Pin N6 | VCCIO4 β I/O bank 4 supply voltage |
| Pin N7 | I/O β User I/O pin (bank 4) |
| Pin N8 | I/O β User I/O pin (bank 4) |
| Pin N9 | I/O β User I/O pin (bank 4) |
| Pin N10 | I/O β User I/O pin (bank 4) |
| Pin P1 | I/O β User I/O pin (bank 4) |
| Pin P2 | I/O β User I/O pin (bank 4) |
| Pin P3 | I/O β User I/O pin (bank 4) |
| Pin P4 | I/O β User I/O pin (bank 4) |
| Pin P5 | I/O β User I/O pin (bank 4) |
| Pin P6 | I/O β User I/O pin (bank 4) |
| Pin P7 | I/O β User I/O pin (bank 4) |
| Pin P8 | I/O β User I/O pin (bank 4) |
| Pin P9 | I/O β User I/O pin (bank 4) |
| Pin P10 | I/O β User I/O pin (bank 4) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM570F100C5N is suitable for 6 applications: Microprocessor Bus Interface Bridging, Address Decoding and Chip-Select Generation, LED Display Scanning and Matrix Control, Peripheral I/O Expansion, Glue Logic Replacement (74-series consolidation), Industrial Control and Automation I/O.
Microprocessor Bus Interface Bridging
The EPM570F100C5N is well suited for bus interface bridging between legacy microprocessors and modern peripherals, where the 76 user I/Os provide ample connections for data, address, and control signals. Its 5.4 ns pin-to-pin delay allows protocol translation at clock rates up to 150 MHz without introducing latency that violates bus hold times. The instant-on Flash configuration eliminates FPGA boot time at power-up, ensuring the bridge is active before the CPU begins its bus cycles. Placed between a CPU local bus and a downstream peripheral, the CPLD decodes chip selects and arbitrates interrupts with deterministic timing. Compared to a small FPGA, the MAX II architecture consumes less static current (typically under 50 mA) while delivering the same glue-logic functionality, making it ideal for cost-sensitive embedded designs.
Recommended
Address Decoding and Chip-Select Generation
The EPM570F100C5N excels at address decoding and chip-select generation in microprocessor systems, where its 440 macrocells can decode wide address buses with multiple chip-select outputs while maintaining 5.4 ns propagation delay. Designers use it to replace discrete 74LS138/139 decoder trees with a single programmable device, reducing PCB area and improving design flexibility. The 76 user I/Os support up to 76 decoded select outputs, well above what any discrete decoder can offer. Multi-volt I/O support (1.8 V, 2.5 V, 3.3 V) lets the CPLD interface directly with both modern low-voltage processors and legacy 3.3 V peripherals without level shifters. The instant-on behavior ensures chip-selects are valid by the time the CPU comes out of reset, eliminating the boot-race conditions common with SRAM-based FPGAs.
Recommended
LED Display Scanning and Matrix Control
The EPM570F100C5N drives multiplexed LED matrix displays by generating row-scan patterns and column data latching signals at rates up to tens of MHz. Its 76 user I/Os can drive a 16-row x 32-column display directly when paired with external LED drivers, and the deterministic 5.4 ns delay allows precise PWM dimming control without flicker. The on-chip 8 Kbit user Flash memory stores calibration coefficients and brightness tables, eliminating an external EEPROM. Designers value the CPLD's ability to combine display refresh logic, button input scanning, and communication interfaces (SPI, I2C) in a single device, reducing BOM cost. The 100-FBGA package's high I/O density is ideal when the display controller must coexist with multiple peripheral interfaces on the same PCB.
Recommended
Peripheral I/O Expansion
The EPM570F100C5N serves as a peripheral I/O expander for microcontrollers or processors that lack sufficient native GPIOs. Its 76 user I/Os can be configured individually as input, output, or bidirectional with internal pull-ups, replacing multiple GPIO expander chips with a single programmable device. The JTAG programming interface allows in-system firmware updates during development without external programming hardware. With MultiVolt I/O support, the CPLD bridges 1.8 V microcontroller pins to 3.3 V peripheral devices without external level shifters. Industrial designers appreciate the deterministic timing for interrupt prioritization and PWM generation at the I/O expansion layer. Compared to I2C/SPI GPIO expanders, the MAX II CPLD delivers faster response (sub-100 ns) and parallel I/O updates across many pins simultaneously.
Recommended
Glue Logic Replacement (74-series consolidation)
The EPM570F100C5N consolidates dozens of 74-series logic gates (AND, OR, XOR, flip-flops, multiplexers) into a single programmable device, dramatically reducing PCB area and BOM count. With 440 macrocells, each equivalent to roughly 4-6 standard 74-series gates, the EPM570 can replace up to 2000 discrete gates while consuming a fraction of the board space. The non-volatile Flash configuration means the logic is active at power-on without external boot devices, eliminating the configuration delay of SRAM FPGAs. Designers can iterate logic changes in seconds via JTAG without re-spinning the PCB, accelerating development cycles. The deterministic 5.4 ns pin-to-pin delay ensures consistent timing across all operating conditions, critical for control-plane logic where race conditions cannot be tolerated.
Recommended
Industrial Control and Automation I/O
The EPM570F100C5N is deployed in industrial control and automation systems where it interfaces sensors, actuators, and communication buses with deterministic timing. Its 76 user I/Os support parallel sensor arrays and multi-channel communication buses (RS-485, RS-232, SPI, I2C), while the 5.4 ns propagation delay enables real-time response to sensor events. For harsh industrial environments, the industrial-grade EPM570F100I5N variant extends operation to -40C to 100C. The CPLD's instant-on behavior ensures deterministic startup of safety-critical control loops, unlike FPGAs that require configuration time at boot. The on-chip 8 Kbit user Flash stores calibration data and serial numbers for asset tracking. Compared to discrete microcontroller solutions, the MAX II CPLD offers faster response and parallel processing of multiple I/O events without software overhead.
Recommended
Recommended Products Summary
Engineering reference data for EPM570F100C5N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM570F100C4N | EPM570F100I5N | EPM570F100A5N | EPM570GF100I5N | EPM570M100C5N | EPM1270F100C5N |
|---|---|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 100-FBGA (11x11 mm) | 100-FBGA (11x11 mm) - same | 100-FBGA (11x11 mm) - same | 100-FBGA (11x11 mm) - same | 100-FBGA (11x11 mm) - same | 100-TFBGA - same footprint | 100-FBGA (11x11 mm) - same |
| Logic Elements | 570 | 570 | 570 | 570 | 570 | 570 | 1270 |
| Macrocells | 440 | 440 | 440 | 440 | 440 | 440 | 980 |
| User I/Os | 76 | 76 | 76 | 76 | 76 | 76 | 76 |
| Propagation Delay (tPD) | 5.4 ns | 4.0 ns (-4 faster) | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns | 5.4 ns |
| Operating Temperature | 0C to 85C (commercial) | 0C to 85C (commercial) | -40C to 100C (industrial) | -40C to 125C (automotive) | -40C to 100C (industrial) | 0C to 85C (commercial) | 0C to 85C (commercial) |
| Core Voltage | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V | 2.5 V / 3.3 V |
| AEC-Q100 Qualified | No | No | No | Yes | No | No | No |
Key Differentiators
- 76 user I/Os in 100-FBGA, the highest I/O-count package in the EPM570 family (vs EPM570T100C5N (TQFP-100, 64 user I/Os))
- On-chip Flash configuration enables instant-on at power-up with no boot PROM (vs SRAM-based FPGAs (e.g., Cyclone IV EP4CE6))
- MultiVolt core allows 2.5 V or 3.3 V core from a single device (vs EPM240T100C5N (MAX II Z, 240 LE, fixed 3.3 V core))
Design Notes
Estimated: The 100-FBGA at 1.0 mm pitch requires PCB fabrication with 0.4 mm laser-drilled microvias or via-in-pad technology for reliable solder joints. Standard 0.3 mm mechanical drills will not fit between 1.0 mm pitch balls; verify your PCB fabricator's capabilities before committing to the BGA variant. Designers can choose the TQFP-100 or EQFP-100 alternatives in the MAX II family for simpler 2-layer PCB designs.
Estimated: The MAX II MultiVolt I/O architecture allows mixing 1.8 V, 2.5 V, and 3.3 V I/O standards across the four I/O banks, but each bank must be powered from a single VCCIO rail. Ensure VCCIO1 through VCCIO4 are properly decoupled with 0.1 uF ceramic capacitors placed within 5 mm of each supply ball, plus a 10 uF bulk capacitor per bank. Unused I/O pins should be configured as outputs driving ground to minimize power consumption and switching noise.
The JTAG chain requires external 4.7 kohm pull-up resistors on TCK and TMS per IEEE 1149.1 specification; missing pull-ups cause intermittent JTAG programming failures. VCCINT must ramp monotonically from 0 V to the target voltage (2.5 V or 3.3 V) within 100 ms to avoid configuration errors at startup. The UFM (User Flash Memory) shares configuration logic resources and must be accounted for in your logic utilization budget before compilation.
Estimated: At maximum toggle rates (76 outputs at 100 MHz with 20 pF loads), the EPM570F100C5N dissipates approximately 0.5 W to 1.0 W typical. The 100-FBGA package has a theta_JA of approximately 30-35 C/W with standard JEDEC test board airflow, resulting in a 15-35 C junction temperature rise above ambient. For enclosed chassis designs without airflow, derate clock frequencies by 25-30% to maintain junction temperature below 125 C.
Compliance Information
RoHS and lead-free compliance confirmed by distributor data. Not AEC-Q100 qualified - migrate to EPM570F100A5N for automotive. Halogen-free and conflict-mineral declarations not specified in available data.
