EPM7128AETC100-7N vs EPM7128AETC100-10 Comparison
Detailed side-by-side comparison of EPM7128AETC100-7N by Altera and EPM7128AETC100-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128AETC100-7N | EPM7128AETC100-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2.5K |
| Logic Array Blocks (LABs) | 4 | 8 |
| User I/Os | 84 | 84 |
| Propagation Delay (tpd) | 7.5 ns | — |
| Counter Frequency (max) | 129.9 MHz | — |
| Internal Frequency (max) | 250 MHz | — |
| Core Supply Voltage | 3.3 V | — |
| Logic Family | CMOS | — |
| Pin Count | 100 | — |
| Package | 100-TQFP | 100-pin TQFP (ET) |
| Mounting Type | Surface Mount | — |
| Operating Temperature | 0 C to +70 C (Commercial) | -40C to +85C (commercial/industrial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Process Technology | 0.30 µm EEPROM CMOS | — |
| Macrocells | — | 128 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (Core) | — | 3.3 V |
| I/O Tolerance | — | 5.0 V tolerant |
| Program Technology | — | EEPROM (in-system programmable) |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Lifecycle Status | — | Obsolete (migrate to MAX II or MAX V) |