EPM7128AETC100-7N - MAX 7000A CPLD, 128 MC, 7.5ns, 100-TQFP | Altera
MPN: EPM7128AETC100-7N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $52.84 | $52.84 |
| 10 | $48.75 | $487.50 |
| 100 | $41.2 | $4,120.00 |
| 500 | $36.55 | $18,275.00 |
| 1,000 | $31.8 | $31,800.00 |
Drop-in alternatives for EPM7128AETC100-7N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC100-5N
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β Drop-Inπ Reference alternative (not in catalog)
EPM7128AETI100-7N
β Drop-Inβ In Stock
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View Datasheet βEPM7128AETC100-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
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View Datasheet βEPM7128AETC100-7N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Device Type | CPLD - Complex Programmable Logic Device |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 4 |
| User I/Os | 84 |
| Propagation Delay (tpd) | 7.5 ns |
| Counter Frequency (max) | 129.9 MHz |
| Internal Frequency (max) | 250 MHz |
| Core Supply Voltage | 3.3 V |
| Logic Family | CMOS |
| Pin Count | 100 |
| Package | 100-TQFP |
| Mounting Type | Surface Mount |
| Operating Temperature | 0 C to +70 C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) / ISP |
| Process Technology | 0.30 Β΅m EEPROM CMOS |
EPM7128AETC100-7N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | TDI β JTAG Test Data In |
| Pin 12 | TMS β JTAG Test Mode Select |
| Pin 13 | TCK β JTAG Test Clock |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | VCC β Core supply voltage (3.3 V) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | GND β Ground |
| Pin 27 | I/O β User I/O pin (bank 2) |
| Pin 28 | I/O β User I/O pin (bank 2) |
| Pin 29 | I/O β User I/O pin (bank 2) |
| Pin 30 | I/O β User I/O pin (bank 2) |
| Pin 31 | I/O β User I/O pin (bank 2) |
| Pin 32 | I/O β User I/O pin (bank 2) |
| Pin 33 | I/O β User I/O pin (bank 2) |
| Pin 34 | I/O β User I/O pin (bank 2) |
| Pin 35 | I/O β User I/O pin (bank 2) |
| Pin 36 | I/O β User I/O pin (bank 2) |
| Pin 37 | GND β Ground |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | I/O β User I/O pin (bank 3) |
| Pin 41 | I/O β User I/O pin (bank 3) |
| Pin 42 | I/O β User I/O pin (bank 3) |
| Pin 43 | I/O β User I/O pin (bank 3) |
| Pin 44 | I/O β User I/O pin (bank 3) |
| Pin 45 | I/O β User I/O pin (bank 3) |
| Pin 46 | I/O β User I/O pin (bank 3) |
| Pin 47 | I/O β User I/O pin (bank 3) |
| Pin 48 | I/O β User I/O pin (bank 3) |
| Pin 49 | I/O β User I/O pin (bank 3) |
| Pin 50 | VCC β Core supply voltage (3.3 V) |
| Pin 51 | I/O β User I/O pin (bank 3) |
| Pin 52 | I/O β User I/O pin (bank 3) |
| Pin 53 | I/O β User I/O pin (bank 3) |
| Pin 54 | I/O β User I/O pin (bank 3) |
| Pin 55 | I/O β User I/O pin (bank 3) |
| Pin 56 | I/O β User I/O pin (bank 3) |
| Pin 57 | I/O β User I/O pin (bank 3) |
| Pin 58 | I/O β User I/O pin (bank 3) |
| Pin 59 | I/O β User I/O pin (bank 3) |
| Pin 60 | I/O β User I/O pin (bank 3) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (bank 4) |
| Pin 63 | I/O β User I/O pin (bank 4) |
| Pin 64 | I/O β User I/O pin (bank 4) |
| Pin 65 | I/O β User I/O pin (bank 4) |
| Pin 66 | I/O β User I/O pin (bank 4) |
| Pin 67 | I/O β User I/O pin (bank 4) |
| Pin 68 | I/O β User I/O pin (bank 4) |
| Pin 69 | I/O β User I/O pin (bank 4) |
| Pin 70 | I/O β User I/O pin (bank 4) |
| Pin 71 | I/O β User I/O pin (bank 4) |
| Pin 72 | I/O β User I/O pin (bank 4) |
| Pin 73 | I/O β User I/O pin (bank 4) |
| Pin 74 | I/O β User I/O pin (bank 4) |
| Pin 75 | GND β Ground |
| Pin 76 | I/O β User I/O pin (bank 4) |
| Pin 77 | I/O β User I/O pin (bank 4) |
| Pin 78 | I/O β User I/O pin (bank 4) |
| Pin 79 | I/O β User I/O pin (bank 4) |
| Pin 80 | I/O β User I/O pin (bank 4) |
| Pin 81 | I/O β User I/O pin (bank 4) |
| Pin 82 | I/O β User I/O pin (bank 4) |
| Pin 83 | I/O β User I/O pin (bank 4) |
| Pin 84 | I/O β User I/O pin (bank 4) |
| Pin 85 | TDO β JTAG Test Data Out |
| Pin 86 | I/O β User I/O pin (bank 1) |
| Pin 87 | I/O β User I/O pin (bank 1) |
| Pin 88 | I/O β User I/O pin (bank 1) |
| Pin 89 | I/O β User I/O pin (bank 1) |
| Pin 90 | I/O β User I/O pin (bank 1) |
| Pin 91 | I/O β User I/O pin (bank 1) |
| Pin 92 | I/O β User I/O pin (bank 1) |
| Pin 93 | I/O β User I/O pin (bank 1) |
| Pin 94 | I/O β User I/O pin (bank 1) |
| Pin 95 | I/O β User I/O pin (bank 1) |
| Pin 96 | I/O β User I/O pin (bank 1) |
| Pin 97 | I/O β User I/O pin (bank 1) |
| Pin 98 | I/O β User I/O pin (bank 1) |
| Pin 99 | GND β Ground |
| Pin 100 | I/O β User I/O pin (bank 1) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETC100-7N is suitable for 6 applications: Legacy Microprocessor Bus Decoding & Address Mapping, Industrial Control State Machines, 5V-to-3.3V System Migration Bridges, Peripheral Glue Logic & ASIC Replacement, Telecom & Networking Interface Bridging, Test & Measurement Instrumentation Front-Ends.
Legacy Microprocessor Bus Decoding & Address Mapping
The EPM7128AETC100-7N's 128 macro cells, 7.5 ns propagation delay, and 84 user I/Os make it well-suited as a glue-logic decoder between microprocessors, memories, and peripherals. In a typical 8086/68000/ARM7 system, the CPLD replaces 3-5 discrete 74LS/74F/GAL chips, decoding chip-select signals and address-mapped registers. The deterministic 7.5 ns tpd across the FastTrack interconnect eliminates timing-variability concerns seen with SRAM-based FPGAs. EEPROM-based instant-on configuration ensures the address map is valid at power-up before the CPU fetches its first instruction, eliminating the boot-PROM overhead required by FPGAs.
Recommended
Industrial Control State Machines
Factory automation controllers, PLCs, and motor-drive boards use the EPM7128AETC100-7N to implement deterministic state machines for sequencing I/O events, PWM generation, and interlock logic. The 129.9 MHz counter frequency supports high-resolution timing and quadrature decoding for encoder feedback. With 84 I/Os, the CPLD can directly interface 24 V opto-isolated field wiring (via external buffers) without intermediate logic. The commercial 0-70 C temperature grade suits cabinet-mounted equipment; for harsher environments the EPM7128AETI100-7N industrial variant is preferred.
Recommended
5V-to-3.3V System Migration Bridges
The MAX 7000A family is pin-compatible with the legacy 5.0 V MAX 7000S family, making the EPM7128AETC100-7N a drop-in 3.3 V replacement for existing 5 V boards. Designers can swap a MAX 7000S EPM7128S for the MAX 7000A EPM7128AETC100-7N on the same PCB footprint to migrate an entire product line to lower-voltage operation, reducing power dissipation by 30-50 percent. The 3.3 V LVTTL/LVCMOS I/O standard directly interfaces modern ASICs, microcontrollers, and DDR memories without external level shifters.
Recommended
Peripheral Glue Logic & ASIC Replacement
In embedded designs where an ASIC or ASSP is unavailable or has been discontinued, the EPM7128AETC100-7N provides a flexible 2,500-gate glue-logic replacement. With 128 macro cells and 84 I/Os, it can implement custom peripherals such as UARTs, SPI/I2C controllers, watchdog timers, and interrupt controllers in a single chip. The JTAG ISP interface allows field firmware updates, while EEPROM non-volatile storage eliminates external boot memory. The CPLD integrates easily into Altera/Intel Quartus development flows for hardware verification.
Recommended
Telecom & Networking Interface Bridging
Telecom line cards, router line-interface modules, and network processors use the EPM7128AETC100-7N to bridge between legacy TTL/CMOS buses and modern SERDES or network-processor interfaces. The 250 MHz internal global clock frequency supports high-speed parallel interfaces up to LVDS-adjacent rates when paired with external transceivers. With 84 I/Os, the CPLD can implement parallel bus multiplexing, parity generation/checking, and clock-domain crossing for multi-protocol systems. JTAG boundary scan supports board-level test access required for telecom-grade assemblies.
Recommended
Test & Measurement Instrumentation Front-Ends
Bench instruments (oscilloscopes, logic analyzers, signal generators) use the EPM7128AETC100-7N to implement channel-switching matrices, trigger logic, and display-timing controllers. The deterministic 7.5 ns tpd simplifies timing closure for multi-channel acquisition paths, and 84 I/Os can mux 8+ analog channels with parallel digital control. EEPROM instant-on behavior ensures the instrument is ready to operate within milliseconds of power-up, an advantage over SRAM FPGAs in production-line test equipment.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETC100-7N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC100-5N | EPM7128AETC100-10N | EPM7128AETC100-7 | EPM7128AETI100-7N |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 100-TQFP | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same | 100-TQFP - same |
| Macro Cells | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tpd) | 7.5 ns | 5 ns (faster) | 10 ns (slower) | 7.5 ns (same) | 7.5 ns (same) |
| Counter Frequency | 129.9 MHz | 175.4 MHz (higher) | 100 MHz (lower) | 129.9 MHz (same) | 129.9 MHz (same) |
| Supply Voltage | 3.3 V | 3.3 V | 3.3 V | 3.3 V | 3.3 V |
| Operating Temperature | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | 0 C to +70 C (Commercial) | -40 C to +85 C (Industrial) |
| Terminal Finish | Lead-free (Pb-free) / N suffix | Lead-free (N suffix) | Lead-free (N suffix) | Legacy Pb finish (no N) | Lead-free (N suffix) |
| User I/Os | 84 | 84 | 84 | 84 | 84 |
Key Differentiators
- Drop-in faster speed grade option exists in identical package (vs EPM7128AETC100-5N)
- Industrial temperature variant available in identical package (vs EPM7128AETI100-7N)
- Pin-compatible with 5 V MAX 7000S for 5 V-to-3.3 V migration (vs EPM7128SQC100-7)
- Non-volatile EEPROM instant-on configuration (vs Generic SRAM FPGA (e.g. Cyclone))
Design Notes
The EPM7128AETC100-7N operates from a single 3.3 V supply (VCC = 3.0 V to 3.6 V). Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin; add a single 10 uF bulk tantalum or ceramic capacitor at the supply entry point. Unlike SRAM FPGAs, the MAX 7000A does not require a separate configuration supply; ICC during normal operation scales with logic utilization and toggle frequency, typically 30-150 mA. During JTAG programming, ISP-pull-up resistors on unused I/Os are automatically enabled and add ~10-20 mA to ICC, which must be considered when budgeting total board power.
The 100-TQFP package uses a 0.5 mm lead pitch on a 14 mm x 14 mm body. Route all signal traces on inner layers to escape the fine-pitch leads; use 0.125 mm (5 mil) traces and 0.125 mm spaces with a solder mask defined (SMD) pad. Place a continuous ground plane on layer 2 directly under the TQFP to provide a low-impedance return path for the high-speed JTAG and clock signals. Maintain at least 4 via connections from the center GND pad (exposed pad not present on this TQFP, but the corner GND pins 26, 37, 61, 75, 99 should each be tied to the ground plane with at least two vias for thermal and electrical performance.
Although the MAX 7000A is a relatively slow device by modern standards (7.5 ns tpd), JTAG clock edges at 10-30 MHz can still produce ringing on TMS/TCK if traces are un-terminated. Keep JTAG chain traces under 50 mm total length and add a 33 ohm series resistor at the TCK driver if ringing is observed. For clock inputs GCLK1-GCLK4, route as 50 ohm controlled-impedance traces and avoid stubs. When the CPLD drives external buses above 30 MHz, place 22-33 ohm series damping resistors within 10 mm of the CPLD output pin to reduce transmission-line reflections.
Common design mistakes include: (1) mixing 5 V signals into the 3.3 V I/O pins (not 5 V tolerant - damage can occur above 3.9 V); (2) leaving JTAG pins floating - TMS and TDI must be pulled up to VCC through 10 kohm resistors to keep the TAP controller in a known state; (3) forgetting that during ISP, all I/O pins have internal pull-ups enabled that may conflict with external pull-down biasing; (4) assuming the EPM7128AETC100-7N is in active production - it is NRND; for new designs use MAX II EPM570 or MAX V 5M240Z. Always design with a footprint-compatible footprint for these modern alternatives when possible.
Compliance Information
The 'N' suffix in EPM7128AETC100-7N denotes Pb-free lead finish per Altera/Intel nomenclature. RoHS and REACH compliance is standard for MAX 7000A -7N variants. Not AEC-Q100 qualified (commercial grade only); AEC-Q100 grade requires separate -10N automotive variant or migration to MAX 10.
