EPM7128AETC144-7 vs EPM7128AETC144-7N Comparison
Detailed side-by-side comparison of EPM7128AETC144-7 by Intel and EPM7128AETC144-7N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ ActiveSpecification Comparison
| Parameter | EPM7128AETC144-7 | EPM7128AETC144-7N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Series | MAX 7000A | — |
| Programmable Type | In-System Programmable (ISP), EEPROM | — |
| Number of Macrocells | 128 | — |
| Number of Logic Array Blocks (LABs) | 8 | — |
| Number of Usable Gates | 2,500 | — |
| Number of I/Os | 100 | — |
| Propagation Delay (tPD) Max | 7.5 ns | — |
| Maximum Operating Frequency | 129.9 MHz | 129.9 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V | 3.3 V |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V tolerant | — |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (commercial) |
| Package | 144-pin TQFP (20x20 mm) | 144-pin TQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) | — |
| Configuration Memory | EEPROM, non-volatile | — |
| ISP Endurance | 100 cycles typical per macrocell | — |
| Process Technology | CMOS | CMOS, EEPROM-based |
| RoHS Status | [DATA_NEEDED: RoHS status] | Compliant |
| Family | — | MAX 7000A |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Logic Gates | — | 2500 (2.5K gates) |
| Macro Cells | — | 128 |
| User I/Os | — | 36 (in 144-pin TQFP) |
| Pin-to-Pin Delay | — | 7.5 ns |
| Propagation Delay (tpd) | — | 7.5 ns |
| Programmability | — | In-System Programmable (ISP) via JTAG |
| Boundary-Scan Test | — | IEEE Std 1149.1 (JTAG) |
| Pin-Compatible With | — | MAX 7000S 5.0V family (144-pin TQFP) |
| Lead-Free | — | Yes |