EPM7128AETC144-7 - 128-Macrocell 7.5ns MAX 7000A CPLD | Intel
MPN: EPM7128AETC144-7 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $24.3 | $24.30 |
| 10 | $22.85 | $228.50 |
| 100 | $20.1 | $2,010.00 |
| 500 | $17.95 | $8,975.00 |
| 1,000 | $16.4 | $16,400.00 |
Drop-in alternatives for EPM7128AETC144-7 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128AETC144-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$21.7 / Unit
View Datasheet →EPM7128AETC144-7N
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$39.82 / Unit
View Datasheet →EPM7128AETI144-7
✅ Drop-In ⚠️ 参数待验证📋 Reference alternative (not in catalog)
EPM7128AETC144-7 Maximum Ratings & Electrical Characteristics
| Series | MAX 7000A |
| Programmable Type | In-System Programmable (ISP), EEPROM |
| Number of Macrocells | 128 |
| Number of Logic Array Blocks (LABs) | 8 |
| Number of Usable Gates | 2,500 |
| Number of I/Os | 100 |
| Propagation Delay (tPD) Max | 7.5 ns |
| Maximum Operating Frequency | 129.9 MHz |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V |
| I/O Voltage (MultiVolt) | 2.5 V / 3.3 V / 5.0 V tolerant |
| Operating Temperature | 0C to +70C (Commercial) |
| Package | 144-pin TQFP (20x20 mm) |
| Mounting Type | Surface Mount |
| Programming Interface | IEEE 1149.1 JTAG (ByteBlaster / USB-Blaster) |
| Configuration Memory | EEPROM, non-volatile |
| ISP Endurance | 100 cycles typical per macrocell |
| Process Technology | CMOS |
EPM7128AETC144-7 144-pin tqfp (20x20 mm) Pin Configuration Guide
Complete pinout information for EPM7128AETC144-7 (144-pin tqfp (20x20 mm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM7128AETC144-7.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETC144-7 is suitable for 6 applications: Microprocessor / Microcontroller Glue Logic, Bus Interface Bridging and Voltage Translation, Industrial Control and State-Machine Controllers, Legacy Peripheral Replacement / 74-Series Consolidation, Power Sequencing and Supervisor Logic, JTAG-Based I/O Expansion and Boundary-Scan Test.
Microprocessor / Microcontroller Glue Logic
The EPM7128AETC144-7 is a classic glue-logic companion for 8/16/32-bit microcontrollers and microprocessors, providing address decoding, chip-select generation, wait-state insertion, and bus arbitration in a single non-volatile device. With 128 macrocells and a 7.5 ns tPD, it can decode a full 24-bit address space in one logic level and still meet a 40 MHz system bus cycle. Unlike an FPGA, the MAX 7000A boots in microseconds without a configuration flash, eliminating the 'blank FPGA at power-up' risk on safety-relevant industrial controllers. Place the device near the CPU and route all control signals with matched-length traces; the JTAG chain doubles as both ISP and boundary-scan test access, reducing test-fixture cost.
Recommended
Bus Interface Bridging and Voltage Translation
The EPM7128AETC144-7's MultiVolt I/O allows it to bridge 5.0 V peripherals to a 3.3 V processor on the same die, replacing discrete 74LVC/74HCT level shifters with a single programmable device. The 100 user I/Os and 128 macrocells are sufficient to implement an 8-bit to 16-bit or 16-bit to 32-bit bus multiplexer/demultiplexer with handshake logic in one part. The 7.5 ns tPD keeps the propagation delay well below one 33 MHz bus cycle, so no wait states are inserted. Designers should power VCCIO at the higher of the two bus voltages to drive 5 V inputs cleanly; series resistors on each I/O line limit inrush during hot-swap.
Recommended
Industrial Control and State-Machine Controllers
Factory automation PLCs and process controllers use the EPM7128AETC144-7 for deterministic state-machine logic such as stepper-motor sequencers, conveyor-index counters, and safety-interlock voters. The 129.9 MHz maximum toggle rate and zero-power EEPROM configuration guarantee deterministic boot, which is essential for IEC 61131-3 and IEC 61508 safety paths. With 100 I/Os the device can directly drive opto-isolated inputs and outputs without a buffer ASIC, and the JTAG port allows in-field firmware updates via the same boundary-scan chain used at board test. Design tip: route GCLK to a dedicated low-jitter oscillator and gate OE1/OE2 only between logic states to avoid bus contention.
Recommended
Legacy Peripheral Replacement / 74-Series Consolidation
The EPM7128AETC144-7 is routinely used to replace stacks of 74HC/74LS glue-logic ICs, freeing PCB area and reducing BOM risk on legacy designs. A single 144-pin TQFP can absorb 10-20 discrete SSI/MSI packages because the 128 macrocells and 100 I/Os comfortably handle address latches, bus transceivers, parity generators, and interrupt-priority encoders. Because the design is captured in HDL (VHDL/Verilog/AHDL) and synthesized in Quartus II / MAX+PLUS II, late ECOs are a software change instead of a board re-spin. Pin migration from discrete logic is straightforward: simply assign 74-series pin functions to the CPLD pins and verify timing closure with the static timing analyzer.
Recommended
Power Sequencing and Supervisor Logic
Power-rail sequencers in telecom and server hardware often use the EPM7128AETC144-7 to generate staggered enables for DC-DC converters and to monitor power-good signals. The 100 I/Os can drive 20-30 enable lines directly with the device's 25 mA IOL capability, while the 7.5 ns tPD allows tight PG-to-EN latency for fast power-up. The non-volatile EEPROM configuration means the sequence is fixed at first power-on, satisfying ATX and SSI power-spec timing budgets without waiting for an FPGA to load. Designers should tie one GCLK input to a precision 100 MHz TCXO and avoid toggling unused I/Os to keep switching noise below the 5 mV/V power-rail tolerance.
Recommended
JTAG-Based I/O Expansion and Boundary-Scan Test
The EPM7128AETC144-7 integrates a 100-channel JTAG-controlled I/O expander that doubles as a boundary-scan test access port, simplifying in-circuit test on dense PCBs. Each macrocell can be steered from the JTAG TAP controller via the USER_INSTRUCTION register, allowing the same device to function as both glue logic and test multiplexer. In production test, the IEEE 1149.1 chain can verify continuity of all 100 I/Os against the netlist, dramatically reducing bed-of-nails fixture cost. Tip: keep TCK < 10 MHz on long JTAG chains and add a 10 kohm pull-up on TCK to prevent floating clocks during cable disconnect events.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETC144-7 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETI144-7 |
|---|---|---|---|---|
| Package | TQFP-144 (20x20 mm) | TQFP-144 (20x20 mm) - same | TQFP-144 (20x20 mm) - same | TQFP-144 (20x20 mm) - same |
| Brand | Intel | Intel | Intel | Intel |
| Speed Grade (tPD max) | 7.5 ns | 10 ns (slower) | 7.5 ns (same) | 7.5 ns (same) |
| Macrocells | 128 | 128 | 128 | 128 |
| User I/Os | 100 | 100 | 100 | 100 |
| Supply Voltage (VCCINT) | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | -40C to +85C (Industrial) |
| Programming Interface | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) | JTAG (IEEE 1149.1) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
| Approximate Unit Price (qty 1) | US$24.30 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Faster speed grade than the standard -10 variant (vs EPM7128AETC144-10)
- Commercial temperature grade - lowest-cost option (vs EPM7128AETC144-7N)
- Largest package density in the EPM7128A 3.3 V family (vs EPM7128AETC100-7N)
Design Notes
Estimated: at VCCINT = 3.3 V, the MAX 7000A core draws approximately 10-30 mA quiescent and up to 200 mA with all 100 I/Os toggling at 100 MHz. Place a 10 uF bulk + 0.1 uF ceramic decoupling pair within 5 mm of each VCCINT/VCCIO pin; in our experience an additional 1 uF X7R near the JTAG VCC pin prevents ByteBlaster programming failures.
The 144-pin TQFP (20x20 mm) has a 0.5 mm pitch. Per IPC-7351 nominal land patterns, allow at least 6 mm of uninterrupted ground plane beneath the package and use 0.25 mm via-in-pad microvias if you must escape from inner pads. The exposed thermal pad is not present on this package, so thermal relief is provided by the ground copper flood only.
Series-terminate each TQFP output with 33 ohm if the trace length exceeds 50 mm or the edge rate is below 3 ns (the 7.5 ns speed grade usually does not require it, but the JTAG TCK line must always be terminated to prevent reflections that fail boundary-scan tests). Keep JTAG signals away from clock traces and add a 10 kohm pull-up on TCK and TMS.
Quartus Prime Web Edition has dropped MAX 7000A support in some 18.x and later releases; verify your toolchain is Quartus II 13.0sp1 or MAX+PLUS II before committing to a new design. Also note that the EPM7128AETC144-7 (commercial) is NOT a drop-in for EPM7128ATC144-12 (5 V MAX 7000S) without redesigning the power tree, because VCCINT is 3.3 V instead of 5 V.
Compliance Information
RoHS, REACH, lead-free, halogen-free, and conflict-mineral status were not present in the verified distributor or datasheet snippets. AEC-Q100 is not applicable because MAX 7000A is not an automotive-qualified family.
