EPM7128AETC144-7N vs EPM7128AETI144-10N Comparison
Detailed side-by-side comparison of EPM7128AETC144-7N by Altera and EPM7128AETI144-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128AETC144-7N - MAX 7000A CPLD, 128 Macros, 144-TQFP | Intel / Altera
EPM7128AETC144-7N ✓ ActiveAltera
EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
EPM7128AETI144-10N ObsoleteSpecification Comparison
| Parameter | EPM7128AETC144-7N | EPM7128AETI144-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 7000A | MAX 7000A |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Logic Gates | 2500 (2.5K gates) | — |
| Macro Cells | 128 | — |
| User I/Os | 36 (in 144-pin TQFP) | — |
| Maximum Operating Frequency | 129.9 MHz | — |
| Pin-to-Pin Delay | 7.5 ns | — |
| Propagation Delay (tpd) | 7.5 ns | — |
| Supply Voltage (VCCINT) | 3.3 V | 3.0 V to 3.6 V (3.3 V nominal) |
| Process Technology | CMOS, EEPROM-based | 0.35 µm CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG | — |
| Boundary-Scan Test | IEEE Std 1149.1 (JTAG) | — |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Package | 144-pin TQFP | TQFP-144 (144-pin) |
| Mounting Type | Surface Mount | Surface Mount |
| Pin-Compatible With | MAX 7000S 5.0V family (144-pin TQFP) | — |
| RoHS Status | Compliant | Compliant |
| Lead-Free | Yes | — |
| Macrocells | — | 128 |
| Usable Gates | — | 2,500 |
| Logic Array Blocks (LABs) | — | 8 |
| Maximum User I/O Pins | — | 100 |
| Propagation Delay (tPD) | — | 10 ns |
| Programming Technology | — | EEPROM (in-system programmable) |
| JTAG Interface | — | IEEE Std 1149.1 BST compliant |
| MSL Level | — | 3 |
| Speed Grade | — | -10 (10 ns tPD) |
| Operating Frequency (fCNT) | — | [DATA_NEEDED: fCNT counter frequency] |