EPM7128AETI144-10N - MAX 7000A CPLD, 128 Macrocells, TQFP-144 | Altera
MPN: EPM7128AETI144-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $33.2 | $332.00 |
| 100 | $28.4 | $2,840.00 |
| 250 | $25.95 | $6,487.50 |
| 500 | $23.1 | $11,550.00 |
Drop-in alternatives for EPM7128AETI144-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM7128AETC144-10N
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AETC144-10
β Drop-Inβ In Stock
$21.7 / Unit
View Datasheet βEPM7128AETC144-7N
β Drop-Inβ In Stock
$39.82 / Unit
View Datasheet βEPM7128AETI144-7
β Drop-Inπ Reference alternative (not in catalog)
EPM7128AETC144-7
β Drop-Inβ In Stock
$16.4 / Unit
View Datasheet βEPM7128AETI144-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000A |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 |
| Maximum User I/O Pins | 100 |
| Propagation Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V nominal) |
| Programming Technology | EEPROM (in-system programmable) |
| JTAG Interface | IEEE Std 1149.1 BST compliant |
| Package | TQFP-144 (144-pin) |
| Operating Temperature | -40C to +85C (industrial) |
| Process Technology | 0.35 Β΅m CMOS EEPROM |
| Mounting Type | Surface Mount |
| MSL Level | 3 |
| RoHS Status | Compliant |
| Speed Grade | -10 (10 ns tPD) |
EPM7128AETI144-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | I/O β User I/O pin (bank 1) |
| Pin 14 | I/O β User I/O pin (bank 1) |
| Pin 15 | I/O β User I/O pin (bank 1) |
| Pin 16 | I/O β User I/O pin (bank 1) |
| Pin 17 | I/O β User I/O pin (bank 1) |
| Pin 18 | I/O β User I/O pin (bank 1) |
| Pin 19 | I/O β User I/O pin (bank 1) |
| Pin 20 | I/O β User I/O pin (bank 1) |
| Pin 21 | I/O β User I/O pin (bank 1) |
| Pin 22 | I/O β User I/O pin (bank 1) |
| Pin 23 | VCCINT β Core supply voltage (3.3 V) |
| Pin 24 | I/O β User I/O pin (bank 1) |
| Pin 25 | I/O β User I/O pin (bank 1) |
| Pin 26 | I/O β User I/O pin (bank 1) |
| Pin 27 | I/O β User I/O pin (bank 1) |
| Pin 28 | I/O β User I/O pin (bank 1) |
| Pin 29 | I/O β User I/O pin (bank 1) |
| Pin 30 | I/O β User I/O pin (bank 1) |
| Pin 31 | I/O β User I/O pin (bank 1) |
| Pin 32 | I/O β User I/O pin (bank 1) |
| Pin 33 | I/O β User I/O pin (bank 1) |
| Pin 34 | GND β Ground |
| Pin 35 | I/O β User I/O pin (bank 1) |
| Pin 36 | I/O β User I/O pin (bank 1) |
| Pin 37 | I/O β User I/O pin (bank 1) |
| Pin 38 | I/O β User I/O pin (bank 1) |
| Pin 39 | I/O β User I/O pin (bank 1) |
| Pin 40 | I/O β User I/O pin (bank 1) |
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| Pin 42 | I/O β User I/O pin (bank 1) |
| Pin 43 | I/O β User I/O pin (bank 1) |
| Pin 44 | I/O β User I/O pin (bank 1) |
| Pin 45 | I/O β User I/O pin (bank 1) |
| Pin 46 | I/O β User I/O pin (bank 1) |
| Pin 47 | VCCIO1 β I/O bank 1 supply voltage (3.3 V) |
| Pin 48 | I/O β User I/O pin (bank 1) |
| Pin 49 | I/O β User I/O pin (bank 1) |
| Pin 50 | I/O β User I/O pin (bank 1) |
| Pin 51 | I/O β User I/O pin (bank 1) |
| Pin 52 | I/O β User I/O pin (bank 1) |
| Pin 53 | I/O β User I/O pin (bank 1) |
| Pin 54 | I/O β User I/O pin (bank 1) |
| Pin 55 | I/O β User I/O pin (bank 1) |
| Pin 56 | I/O β User I/O pin (bank 1) |
| Pin 57 | I/O β User I/O pin (bank 1) |
| Pin 58 | I/O β User I/O pin (bank 1) |
| Pin 59 | I/O β User I/O pin (bank 1) |
| Pin 60 | I/O β User I/O pin (bank 1) |
| Pin 61 | I/O β User I/O pin (bank 2) |
| Pin 62 | GND β Ground |
| Pin 63 | I/O β User I/O pin (bank 2) |
| Pin 64 | I/O β User I/O pin (bank 2) |
| Pin 65 | I/O β User I/O pin (bank 2) |
| Pin 66 | I/O β User I/O pin (bank 2) |
| Pin 67 | I/O β User I/O pin (bank 2) |
| Pin 68 | I/O β User I/O pin (bank 2) |
| Pin 69 | I/O β User I/O pin (bank 2) |
| Pin 70 | I/O β User I/O pin (bank 2) |
| Pin 71 | I/O β User I/O pin (bank 2) |
| Pin 72 | I/O β User I/O pin (bank 2) |
| Pin 73 | VCCIO2 β I/O bank 2 supply voltage (3.3 V) |
| Pin 74 | I/O β User I/O pin (bank 2) |
| Pin 75 | I/O β User I/O pin (bank 2) |
| Pin 76 | I/O β User I/O pin (bank 2) |
| Pin 77 | I/O β User I/O pin (bank 2) |
| Pin 78 | I/O β User I/O pin (bank 2) |
| Pin 79 | I/O β User I/O pin (bank 2) |
| Pin 80 | I/O β User I/O pin (bank 2) |
| Pin 81 | TDO β JTAG test data output |
| Pin 82 | TMS β JTAG test mode select |
| Pin 83 | TDI β JTAG test data input |
| Pin 84 | TCK β JTAG test clock |
| Pin 85 | I/O β User I/O pin (bank 2) |
| Pin 86 | GND β Ground |
| Pin 87 | I/O β User I/O pin (bank 2) |
| Pin 88 | I/O β User I/O pin (bank 2) |
| Pin 89 | I/O β User I/O pin (bank 2) |
| Pin 90 | I/O β User I/O pin (bank 2) |
| Pin 91 | I/O β User I/O pin (bank 2) |
| Pin 92 | I/O β User I/O pin (bank 2) |
| Pin 93 | I/O β User I/O pin (bank 2) |
| Pin 94 | I/O β User I/O pin (bank 2) |
| Pin 95 | I/O β User I/O pin (bank 2) |
| Pin 96 | I/O β User I/O pin (bank 2) |
| Pin 97 | I/O β User I/O pin (bank 2) |
| Pin 98 | I/O β User I/O pin (bank 2) |
| Pin 99 | I/O β User I/O pin (bank 2) |
| Pin 100 | I/O β User I/O pin (bank 2) |
| Pin 101 | GCLK1 β Global clock input 1 |
| Pin 102 | GCLK2 β Global clock input 2 |
| Pin 103 | GCLK3 β Global clock input 3 |
| Pin 104 | GCLRn β Global clear (active low) |
| Pin 105 | OE1 β Output enable 1 |
| Pin 106 | OE2 β Output enable 2 |
| Pin 107 | I/O β User I/O pin (bank 2) |
| Pin 108 | I/O β User I/O pin (bank 2) |
| Pin 109 | I/O β User I/O pin (bank 2) |
| Pin 110 | I/O β User I/O pin (bank 2) |
| Pin 111 | VCCINT β Core supply voltage (3.3 V) |
| Pin 112 | I/O β User I/O pin (bank 2) |
| Pin 113 | I/O β User I/O pin (bank 2) |
| Pin 114 | I/O β User I/O pin (bank 2) |
| Pin 115 | I/O β User I/O pin (bank 2) |
| Pin 116 | I/O β User I/O pin (bank 2) |
| Pin 117 | I/O β User I/O pin (bank 2) |
| Pin 118 | I/O β User I/O pin (bank 2) |
| Pin 119 | I/O β User I/O pin (bank 2) |
| Pin 120 | I/O β User I/O pin (bank 2) |
| Pin 121 | I/O β User I/O pin (bank 2) |
| Pin 122 | I/O β User I/O pin (bank 2) |
| Pin 123 | I/O β User I/O pin (bank 2) |
| Pin 124 | I/O β User I/O pin (bank 2) |
| Pin 125 | GND β Ground |
| Pin 126 | I/O β User I/O pin (bank 2) |
| Pin 127 | I/O β User I/O pin (bank 2) |
| Pin 128 | I/O β User I/O pin (bank 2) |
| Pin 129 | I/O β User I/O pin (bank 2) |
| Pin 130 | I/O β User I/O pin (bank 2) |
| Pin 131 | I/O β User I/O pin (bank 2) |
| Pin 132 | I/O β User I/O pin (bank 2) |
| Pin 133 | I/O β User I/O pin (bank 2) |
| Pin 134 | I/O β User I/O pin (bank 2) |
| Pin 135 | I/O β User I/O pin (bank 2) |
| Pin 136 | I/O β User I/O pin (bank 2) |
| Pin 137 | I/O β User I/O pin (bank 2) |
| Pin 138 | VCCIO2 β I/O bank 2 supply voltage (3.3 V) |
| Pin 139 | I/O β User I/O pin (bank 2) |
| Pin 140 | I/O β User I/O pin (bank 2) |
| Pin 141 | I/O β User I/O pin (bank 2) |
| Pin 142 | I/O β User I/O pin (bank 2) |
| Pin 143 | I/O β User I/O pin (bank 2) |
| Pin 144 | I/O β User I/O pin (bank 2) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128AETI144-10N is suitable for 6 applications: PCI/ISA Bus Interface Bridging, Microcontroller/DSP Glue Logic, Address Decoding & Memory Mapping, Industrial Control State Machines, Communication Protocol Bridging, Legacy Peripheral Expansion Boards.
PCI/ISA Bus Interface Bridging
The EPM7128AETI144-10N fits PCI/ISA bus bridging because its 128 macrocells and 100 user I/O pins can implement address latches, data buffers, and command decoders for legacy peripheral expansion. With a 10 ns tPD, the device meets the 33 MHz PCI clock-to-output budget with comfortable margin, while 5 V tolerant inputs on 3.3 V VCCIO allow direct interfacing to 5 V ISA slots. The on-chip EEPROM eliminates boot ROMs and reduces board area. Companion devices include the Altera MAX 7000A family members with larger I/O counts for fan-out.
Recommended
Microcontroller/DSP Glue Logic
The EPM7128AETI144-10N provides deterministic glue logic between microcontrollers, DSPs, and external peripherals. Its 128 macrocells are sufficient for chip-select decoding, wait-state generation, and interrupt steering, while the 10 ns propagation delay ensures setup/hold margins in high-speed DSP interfaces. JTAG-based in-system programmability enables late-stage board revisions without re-spinning the PCB, and the industrial -40C to +85C rating suits automotive under-hood and factory-floor controllers.
Recommended
Address Decoding & Memory Mapping
The EPM7128AETI144-10N is well-suited for address decoding in systems that map multiple memory banks, peripherals, or dual-port RAM. With 128 macrocells, the device can decode 24-bit or wider address buses and produce chip-select outputs in a single pass, while 5 V tolerant inputs on 3.3 V VCCIO allow interfacing to legacy 5 V memory buses. The 10 ns tPD fits comfortably inside typical memory access cycles of 30-50 ns, leaving timing margin for bus arbitration logic.
Recommended
Industrial Control State Machines
The EPM7128AETI144-10N delivers robust Moore/Mealy state machines for industrial control and instrumentation. Its EEPROM-based configuration means the device retains state at power-up without external boot memory - critical for deterministic startup sequences in process-control PLCs. The industrial -40C to +85C operating range covers factory-floor conditions, and 100 user I/O pins support multi-axis stepper/servo control with limit-switch monitoring and encoder feedback in a single chip.
Recommended
Communication Protocol Bridging
The EPM7128AETI144-10N bridges asynchronous and synchronous communication protocols such as UART, SPI, I2C, and parallel DSP HPI by implementing framing, CRC, and clock-domain crossing in programmable logic. The 10 ns tPD supports SPI clock rates above 30 MHz, and 100 user I/O pins allow multiple concurrent bridges to coexist. JTAG in-system programmability enables field firmware updates to support evolving protocol revisions.
Recommended
Legacy Peripheral Expansion Boards
The EPM7128AETI144-10N serves as a feature-rich I/O expander on legacy peripheral expansion boards where microcontrollers lack sufficient pins. With 100 user I/O pins and 128 macrocells, a single device can implement dozens of PWM channels, quadrature decoders, and GPIO extenders. Industrial temperature range and JTAG field programmability make it a long-life-cycle choice for industrial backplane and test-and-measurement expansion cards.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128AETI144-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128AETC144-10N | EPM7128AETC144-10 | EPM7128AETC144-7N | EPM7128AETI144-7 | EPM7128AETC144-7 |
|---|---|---|---|---|---|---|
| Package | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 | TQFP-144 |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 10 ns | 7.5 ns | 7 ns | 7 ns |
| Temperature Grade | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial (0C to +70C) |
| Supply Voltage | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V | 3.0-3.6 V |
| Max User I/O | 100 | 100 | 100 | 100 | 100 | 100 |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes | Yes | Yes |
| Family | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A | MAX 7000A |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature range with 10 ns speed grade (vs EPM7128AETC144-10N)
- Faster propagation delay available in same package (vs EPM7128AETI144-7)
- Drop-in compatibility across the MAX 7000A TQFP-144 family (vs EPM570T144C5N)
Design Notes
Estimated: at VCCINT=3.3 V with 128 macrocells switching at 50 MHz, Icc is approximately 80-120 mA depending on output loading. Decouple VCCINT and VCCIO pins with one 0.1 uF X7R ceramic capacitor per supply pin plus a single 10 uF bulk capacitor near the device. Place the bulk capacitor within 5 mm of the closest VCC pin to suppress switching transients during ISP programming.
Route the four GCLK pins (GCLK1-GCLK3 and the dedicated clock/clear) on impedance-controlled traces with matched lengths (within 0.5 inches / 12 mm) to minimize clock skew. Keep JTAG signals (TCK, TMS, TDI, TDO) away from high-speed I/O switching lines to avoid coupling noise during in-system programming. Follow Altera's TQFP-144 land pattern with 0.5 mm pitch and 4 inner power/ground thermal vias under the exposed die attach pad.
The EPM7128AETI144-10N supports 5 V tolerant inputs on a 3.3 V VCCIO rail because the I/O cells use a dual-oxide process. When interfacing to 5 V logic, do not exceed the absolute maximum input voltage of 5.5 V and add 10 kohm series resistors on inputs that share a bus with hot-plug connectors. Outputs are 3.3 V CMOS; drive 5 V CMOS inputs through a 74HCT244 buffer if voltage translation is required.
Do not assume JTAG IDs are identical across speed grades - the BSDL file must be regenerated for each variant. Avoid using both OE1 and OE2 as global output enables if they have different timing - assign fast signals to OE1. When migrating from MAX 7000 to MAX II (EPM570), note that the JTAG instruction set and pinout differ; full PCB rework is required.
Compliance Information
RoHS and REACH compliant per Altera/Intel product declaration. Lead-free matte-tin terminations, halogen-free molding compound. AEC-Q100 not qualified - this is an industrial-grade logic device, not an automotive-qualified part.
