EPM7128SQC100-10N vs EPM7128SQC100-7 Comparison
Detailed side-by-side comparison of EPM7128SQC100-10N by Altera and EPM7128SQC100-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 ObsoleteSpecification Comparison
| Parameter | EPM7128SQC100-10N | EPM7128SQC100-7 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Obsolete |
| Family | MAX 7000 | MAX 7000S |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) | — |
| User I/O Pins | 84 | — |
| Propagation Delay (tPD) | 10 ns | 7.5 ns |
| Maximum Frequency | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) | — |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) | — |
| Package | 100-pin PQFP (BQFP) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin | JTAG (IEEE Std 1149.1), in-system programmable |
| Operating Temperature | -40C to +85C (industrial) | [DATA_NEEDED: operating temperature range] |
| Mounting Type | Surface Mount | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) | — |
| Architecture Generation | Second-generation MAX | — |
| Product Type | — | CPLD - Complex Programmable Logic Device |
| User I/Os | — | 84 |
| Logic Elements / LABs | — | 4 Logic Array Blocks (LABs) |
| Maximum Internal Frequency | — | 125 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Technology | — | CMOS, EEPROM-based, non-volatile |
| RoHS Status | — | Non-RoHS (legacy SnPb package) |