EPM7128SQC100-10N - MAX 7000 128-Macro-Cell CPLD, 10ns | Altera
MPN: EPM7128SQC100-10N β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $22.55 | $22.55 |
| 10 | $20.5 | $205.00 |
| 100 | $18.25 | $1,825.00 |
| 500 | $16.4 | $8,200.00 |
| 1,000 | $14.95 | $14,950.00 |
Drop-in alternatives for EPM7128SQC100-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
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View Datasheet βEPM7128SQC100-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macro cells each) |
| User I/O Pins | 84 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency | 100 MHz |
| Supply Voltage (VCCINT) | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | 3.3 V or 5 V (MultiVolt interface) |
| Package | 100-pin PQFP (BQFP) |
| Configuration Memory | EEPROM (non-volatile) |
| Programming Interface | JTAG (IEEE Std 1149.1), 4-pin |
| Operating Temperature | -40C to +85C (industrial) |
| Mounting Type | Surface Mount |
| Lead-Free / RoHS Status | Lead-free (N suffix) |
| Architecture Generation | Second-generation MAX |
EPM7128SQC100-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (general purpose) |
| Pin 2 | I/O β User I/O pin (general purpose) |
| Pin 3 | I/O β User I/O pin (general purpose) |
| Pin 4 | I/O β User I/O pin (general purpose) |
| Pin 5 | I/O β User I/O pin (general purpose) |
| Pin 6 | I/O β User I/O pin (general purpose) |
| Pin 7 | I/O β User I/O pin (general purpose) |
| Pin 8 | I/O β User I/O pin (general purpose) |
| Pin 9 | VCC β 5V supply |
| Pin 10 | I/O β User I/O pin (general purpose) |
| Pin 11 | I/O β User I/O pin (general purpose) |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin (general purpose) |
| Pin 14 | I/O β User I/O pin (general purpose) |
| Pin 15 | I/O β User I/O pin (general purpose) |
| Pin 16 | I/O β User I/O pin (general purpose) |
| Pin 17 | I/O β User I/O pin (general purpose) |
| Pin 18 | I/O β User I/O pin (general purpose) |
| Pin 19 | I/O β User I/O pin (general purpose) |
| Pin 20 | I/O β User I/O pin (general purpose) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (general purpose) |
| Pin 23 | I/O β User I/O pin (general purpose) |
| Pin 24 | I/O β User I/O pin (general purpose) |
| Pin 25 | I/O β User I/O pin (general purpose) |
| Pin 26 | I/O β User I/O pin (general purpose) |
| Pin 27 | I/O β User I/O pin (general purpose) |
| Pin 28 | VCC β 5V supply |
| Pin 29 | I/O β User I/O pin (general purpose) |
| Pin 30 | I/O β User I/O pin (general purpose) |
| Pin 31 | GND β Ground |
| Pin 32 | I/O β User I/O pin (general purpose) |
| Pin 33 | I/O β User I/O pin (general purpose) |
| Pin 34 | I/O β User I/O pin (general purpose) |
| Pin 35 | I/O β User I/O pin (general purpose) |
| Pin 36 | I/O β User I/O pin (general purpose) |
| Pin 37 | I/O β User I/O pin (general purpose) |
| Pin 38 | I/O β User I/O pin (general purpose) |
| Pin 39 | I/O β User I/O pin (general purpose) |
| Pin 40 | I/O β User I/O pin (general purpose) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (general purpose) |
| Pin 43 | I/O β User I/O pin (general purpose) |
| Pin 44 | I/O β User I/O pin (general purpose) |
| Pin 45 | I/O β User I/O pin (general purpose) |
| Pin 46 | I/O β User I/O pin (general purpose) |
| Pin 47 | I/O β User I/O pin (general purpose) |
| Pin 48 | VCC β 5V supply |
| Pin 49 | I/O β User I/O pin (general purpose) |
| Pin 50 | I/O β User I/O pin (general purpose) |
| Pin 51 | GND β Ground |
| Pin 52 | INPUT/GCLK β Global clock input / dedicated input |
| Pin 53 | INPUT/OE2 β Output enable 2 / dedicated input |
| Pin 54 | INPUT/OE1 β Output enable 1 / dedicated input |
| Pin 55 | INPUT/CLR β Clear / dedicated input |
| Pin 56 | I/O β User I/O pin (general purpose) |
| Pin 57 | I/O β User I/O pin (general purpose) |
| Pin 58 | I/O β User I/O pin (general purpose) |
| Pin 59 | I/O β User I/O pin (general purpose) |
| Pin 60 | I/O β User I/O pin (general purpose) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (general purpose) |
| Pin 63 | I/O β User I/O pin (general purpose) |
| Pin 64 | I/O β User I/O pin (general purpose) |
| Pin 65 | I/O β User I/O pin (general purpose) |
| Pin 66 | I/O β User I/O pin (general purpose) |
| Pin 67 | I/O β User I/O pin (general purpose) |
| Pin 68 | I/O β User I/O pin (general purpose) |
| Pin 69 | VCC β 5V supply |
| Pin 70 | I/O β User I/O pin (general purpose) |
| Pin 71 | I/O β User I/O pin (general purpose) |
| Pin 72 | GND β Ground |
| Pin 73 | I/O β User I/O pin (general purpose) |
| Pin 74 | I/O β User I/O pin (general purpose) |
| Pin 75 | I/O β User I/O pin (general purpose) |
| Pin 76 | I/O β User I/O pin (general purpose) |
| Pin 77 | I/O β User I/O pin (general purpose) |
| Pin 78 | I/O β User I/O pin (general purpose) |
| Pin 79 | I/O β User I/O pin (general purpose) |
| Pin 80 | I/O β User I/O pin (general purpose) |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β User I/O pin (general purpose) |
| Pin 83 | I/O β User I/O pin (general purpose) |
| Pin 84 | I/O β User I/O pin (general purpose) |
| Pin 85 | I/O β User I/O pin (general purpose) |
| Pin 86 | I/O β User I/O pin (general purpose) |
| Pin 87 | I/O β User I/O pin (general purpose) |
| Pin 88 | VCC β 5V supply |
| Pin 89 | I/O β User I/O pin (general purpose) |
| Pin 90 | I/O β User I/O pin (general purpose) |
| Pin 91 | GND β Ground |
| Pin 92 | I/O β User I/O pin (general purpose) |
| Pin 93 | TDI β JTAG Test Data In |
| Pin 94 | TMS β JTAG Test Mode Select |
| Pin 95 | TCK β JTAG Test Clock |
| Pin 96 | TDO β JTAG Test Data Out |
| Pin 97 | I/O β User I/O pin (general purpose) |
| Pin 98 | I/O β User I/O pin (general purpose) |
| Pin 99 | I/O β User I/O pin (general purpose) |
| Pin 100 | I/O β User I/O pin (general purpose) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC100-10N is suitable for 6 applications: Industrial Control Glue Logic, Address Decoding and Bus Interfacing, Telecommunications Equipment Logic, Legacy 5V System Designs, State Machine and FSM Implementation, Peripheral Interfacing Bridges.
Industrial Control Glue Logic
The EPM7128SQC100-10N serves as deterministic glue logic in industrial PLC and motor-control systems, where its 128 macro cells, 84 user I/Os, and 10ns tPD meet the timing requirements for bus arbitration and signal conditioning. The instant-on non-volatile EEPROM configuration eliminates boot time and external PROM, while the -40C to +85C industrial temperature range supports factory-floor operation. Place the CPLD between a microcontroller and peripheral bus to implement custom decode, latch, and handshake logic with deterministic pin-to-pin delay - critical for hard-real-time control loops where FPGA variability would be unacceptable.
Recommended
Address Decoding and Bus Interfacing
In embedded CPU systems, the EPM7128SQC100-10N implements address decoding and peripheral chip-select generation with 10ns propagation delay, well within typical 8/16-bit microcontroller bus cycles. The 128 macro cells comfortably handle complex decode trees across multiple peripheral devices, while the MultiVolt I/O interface connects directly to 3.3V MCUs without level shifters. Each LAB (Logic Array Block) of 16 macro cells can be assigned to a separate peripheral bus, and the deterministic tPD ensures zero-wait-state operation across the full industrial temperature range.
Recommended
Telecommunications Equipment Logic
The EPM7128SQC100-10N provides non-volatile, deterministic logic for telecommunications line cards and backplane controllers where instant-on behavior is essential. Its 84 I/Os are well suited to LVCMOS or TTL-level backplane signaling, and the JTAG interface per IEEE 1149.1 enables board-level boundary-scan testing to verify interconnect integrity during manufacturing. The 5V supply tolerance (4.75V to 5.25V) aligns with traditional telecom -48V isolated supply rails, and the 10ns tPD supports legacy telecom timing budgets at line-card interface speeds.
Recommended
Legacy 5V System Designs
For systems requiring 5V core operation (such as legacy ISA-bus cards, VME boards, or older industrial controllers), the EPM7128SQC100-10N provides 128 macro cells at 5V VCCINT with 3.3V/5V tolerant I/Os via MultiVolt. Most modern FPGAs operate only at lower core voltages and cannot interface directly to 5V systems without level shifters, making the CPLD the right choice. The non-volatile EEPROM configuration also eliminates the boot PROM required by SRAM-based FPGAs, reducing BOM cost and board area in legacy designs.
Recommended
State Machine and FSM Implementation
The EPM7128SQC100-10N implements complex state machines for protocol converters, sequencers, and control logic with deterministic timing that FPGA block-RAM-driven FSMs cannot match. Each macro cell contains a programmable flip-flop and product-term select matrix, supporting one-hot, binary, or Gray-coded state machines with 10ns clock-to-output delay. The 100 MHz fMAX supports high-speed protocol conversion in serial-communication bridges, while 84 I/Os accommodate multi-channel state machines in parallel control systems.
Recommended
Peripheral Interfacing Bridges
The EPM7128SQC100-10N bridges mismatched peripherals in mixed-voltage systems, converting 5V parallel buses to 3.3V SPI or vice versa. Its 84 user I/Os and MultiVolt interface handle wide parallel buses (up to 32-bit data plus control signals) with 10ns propagation delay. The EEPROM configuration is non-volatile, so bridges survive power cycles without reconfiguration, and JTAG boundary-scan simplifies production testing of bridge-equipped boards. The 100-pin PQFP package provides sufficient I/O for full 32-bit bridging with handshake lines.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC100-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC100-10F | EPM7128SQC100-10 | EPM7128AETC100-10N | EPM7128AETC100-10 | EPM7128BTC100-10 |
|---|---|---|---|---|---|---|
| Package | 100-pin PQFP | 100-pin PQFP - same | 100-pin PQFP - same | 100-pin TQFP/PQFP - same | 100-pin TQFP/PQFP - same | 100-pin BQFP - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Macro Cells | 128 | 128 - same | 128 - same | 128 - same | 128 - same | 128 - same |
| Propagation Delay (tPD) | 10 ns | 10 ns - same | 10 ns - same | 10 ns - same | 10 ns - same | 10 ns - same |
| RoHS Compliance (N suffix) | Yes (N suffix) | Yes (N suffix implied) | No (leaded) | Yes (N suffix) | No (leaded) | No (leaded) |
| Core Voltage | 5 V | 5 V - same | 5 V - same | 5 V (MAX 7000S) | 5 V (MAX 7000S) | 5 V (MAX 7000B) |
| Family / Series | MAX 7000 | MAX 7000 - same | MAX 7000 - same | MAX 7000S | MAX 7000S | MAX 7000B |
| User I/O Pins | 84 | 84 - same | 84 - same | 84 - same | 84 - same | 84 - same |
| Maximum Frequency | 100 MHz | 100 MHz - same | 100 MHz - same | 100 MHz - same | 100 MHz - same | 100 MHz - same |
Key Differentiators
- 100 MHz maximum operating frequency across full industrial temperature range (vs EPM7128SQC100-15N)
- RoHS-compliant lead-free (N suffix) manufacturing (vs EPM7128SQC100-10)
- Same-family pin-to-pin drop-in compatible with MAX 7000S and MAX 7000B series (vs EPM7128AETC100-10N)
Design Notes
The EPM7128SQC100-10N requires a stable 5V (4.75V to 5.25V) supply on VCCINT pins (9, 28, 48, 69, 88). Place 0.1uF ceramic decoupling capacitors as close as possible to each VCC pin, and add a bulk 10uF tantalum or aluminum electrolytic capacitor at the supply entry. The MultiVolt I/O interface supports 3.3V signaling at the I/O pins while the core operates at 5V - do not mix VCCIO and VCCINT, as the device uses a single 5V rail for both. Avoid powering up with VCC below 4.5V to prevent partial EEPROM configuration corruption.
The 100-pin PQFP package has 0.65 mm pitch gull-wing leads; route all signals on inner PCB layers and use a ground plane on the layer directly beneath the device to minimize EMI. JTAG signals (TCK pin 95, TMS pin 94, TDI pin 93, TDO pin 96) must be routed with 4-8 mil traces and kept short, with TCK having a series 100 ohm termination if the cable exceeds 100 mm. Add 10k ohm pull-ups on TDI, TMS, and TCK to prevent spurious JTAG entry during power-up. Decouple each VCC pin with a separate 0.1uF capacitor - do not share capacitors between adjacent VCC pins.
Do not confuse the EPM7128SQC100-10N with the EPM7128SQC100-7 (faster 7ns variant) or EPM7128SQC100-15N (slower 15ns variant) - the tPD suffix is critical for timing closure. The 'N' suffix indicates RoHS-compliant lead-free manufacturing; the non-N suffix indicates tin-lead finish and is not RoHS compliant. Always use MAX+PLUS II or Quartus Prime software with the correct device family library (max7000) selected; using a generic 'CPLD' library can generate incompatible programming files. The dedicated INPUT/GCLK, INPUT/OE2, INPUT/OE1, and INPUT/CLR pins (52-55) cannot be used as general-purpose I/O - they serve only as global clock, output enable, and clear signals.
Compliance Information
RoHS compliance indicated by 'N' suffix in part number per Altera naming convention. AEC-Q100 not applicable as this is a CPLD not intended for automotive safety-critical applications. REACH compliance assumed per standard Altera product compliance policy.
