EPM7128SQC100-6 vs EPM7128SQC100-10N Comparison
Detailed side-by-side comparison of EPM7128SQC100-6 by Intel and EPM7128SQC100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7128SQC100-6 | EPM7128SQC100-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Active | Active |
| Family | MAX 7000S | MAX 7000 |
| Logic Family | CMOS (EEPROM-based) | — |
| Macrocells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | — |
| Number of Pins | 100 | — |
| Package | PQFP-100 (SQC), 100-BQFP | 100-pin PQFP (BQFP) |
| Propagation Delay (tPD) | 6 ns | 10 ns |
| Internal Frequency | 147.1 MHz | — |
| Supply Voltage | 5 V | — |
| Operating Temperature | 0C to +70C (commercial) | -40C to +85C (industrial) |
| Programmable via | JTAG (IEEE 1149.1) ISP | — |
| Memory Type | Non-volatile EEPROM | — |
| Mounting Type | Surface Mount (Tray) | Surface Mount |
| RoHS Status | [DATA_NEEDED: rohs status] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 (16 macro cells each) |
| User I/O Pins | — | 84 |
| Maximum Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V (4.75 V to 5.25 V) |
| I/O Voltage Tolerance | — | 3.3 V or 5 V (MultiVolt interface) |
| Configuration Memory | — | EEPROM (non-volatile) |
| Programming Interface | — | JTAG (IEEE Std 1149.1), 4-pin |
| Lead-Free / RoHS Status | — | Lead-free (N suffix) |
| Architecture Generation | — | Second-generation MAX |