EPM7128SQC100-7 vs EPM7128SQC100-10F Comparison
Detailed side-by-side comparison of EPM7128SQC100-7 by Intel and EPM7128SQC100-10F by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 ObsoleteAltera
EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
EPM7128SQC100-10F ✓ ActiveSpecification Comparison
| Parameter | EPM7128SQC100-7 | EPM7128SQC100-10F |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Active |
| Product Type | CPLD - Complex Programmable Logic Device | CPLD (Complex Programmable Logic Device) |
| Family | MAX 7000S | MAX 7000S |
| Macro Cells | 128 | — |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | 84 |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Maximum Internal Frequency | 125 MHz | — |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | — |
| Technology | CMOS, EEPROM-based, non-volatile | — |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (Plastic Quad Flat Pack) |
| Programming Interface | JTAG (IEEE Std 1149.1), in-system programmable | — |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Non-RoHS (legacy SnPb package) | Compliant (F suffix variant) |
| Macrocells | — | 128 |
| Logic Array Blocks (LABs) | — | 8 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5 V |
| Process Technology | — | CMOS EEPROM |
| Programmability | — | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Lead-Free (F suffix) | — | Yes (Pb-free finish) |