EPM7128SQC100-10F - 128-Macrocell MAX 7000 CPLD, 10ns, 100-PQFP | Altera (Intel)
MPN: EPM7128SQC100-10F β Active| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $7.95 | $7.95 |
| 10 | $7.1 | $71.00 |
| 100 | $6.25 | $625.00 |
| 500 | $5.55 | $2,775.00 |
| 1,000 | $4.95 | $4,950.00 |
Drop-in alternatives for EPM7128SQC100-10F β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM7128SQC100-10F Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 2,500 |
| Macrocells | 128 |
| Logic Array Blocks (LABs) | 8 |
| User I/Os | 84 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Counter Frequency | 100 MHz |
| Supply Voltage (VCCINT) | 5 V |
| Process Technology | CMOS EEPROM |
| Programmability | In-System Programmable (ISP) via JTAG (IEEE 1149.1) |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) |
| Lead-Free (F suffix) | Yes (Pb-free finish) |
| RoHS Status | Compliant (F suffix variant) |
EPM7128SQC100-10F Pin Configuration
| Pin 1 | I/O β User I/O pin |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
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| Pin 9 | I/O β User I/O pin |
| Pin 10 | GND β Ground |
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| Pin 19 | I/O β User I/O pin |
| Pin 20 | GND β Ground |
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| Pin 30 | GND β Ground |
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| Pin 40 | GND β Ground |
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| Pin 50 | GND β Ground |
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| Pin 59 | I/O β User I/O pin |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O pin |
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| Pin 69 | I/O β User I/O pin |
| Pin 70 | GND β Ground |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | TDI β JTAG Test Data In |
| Pin 79 | TMS β JTAG Test Mode Select |
| Pin 80 | TCK β JTAG Test Clock |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
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| Pin 84 | I/O β User I/O pin |
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| Pin 88 | I/O β User I/O pin |
| Pin 89 | I/O β User I/O pin |
| Pin 90 | GND β Ground |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | TDO β JTAG Test Data Out |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC100-10F is suitable for 6 applications: 5V Industrial Glue Logic and Bus Interfacing, Address Decoding and Chip-Select Generation, Peripheral Control for 5V Microcontrollers, Legacy 74-Series TTL/CMOS Logic Replacement, State-Machine and Sequencer Logic in Industrial Automation, Telecommunications Backplane Glue Logic.
5V Industrial Glue Logic and Bus Interfacing
The EPM7128SQC100-10F is a strong fit for 5 V industrial glue-logic and bus-bridge applications because it delivers 128 macrocells with 84 user I/Os in the 100-PQFP footprint, and operates from a single 5 V supply. Compared with discrete 74-series TTL gates, the part consolidates address decoding, chip-select generation, and bus arbitration into one in-system programmable device, reducing board area and BOM count. The 10 ns pin-to-pin delay supports ISA-style bus cycles (8 MHz) and VME-style handshakes with deterministic timing that simplifies timing closure. Engineers typically place the CPLD between a 5 V microcontroller and legacy peripheral ICs, programming it once via JTAG with Quartus or MAX+PLUS II. This design is also well suited to long-lifecycle industrial automation where discrete logic must be replaced during a board refresh without redesigning the backplane.
Recommended
Address Decoding and Chip-Select Generation
The EPM7128SQC100-10F excels at address decoding and chip-select generation for memory-mapped buses such as ISA, PC/104, and VME. The 128 macrocells provide enough logic capacity to decode 24-bit address ranges with multiple chip-select outputs, and the 10 ns tPD keeps the decoder in the same clock cycle as the address latch. Designers typically build a single in-system programmable device that generates chip-enables for SRAM, ROM, and peripheral chips on a 5 V CPU board, replacing discrete 74LS138/139/151 trees. The non-volatile EEPROM cells ensure correct chip-select mapping immediately on power-up, which is critical for boot memory and BIOS chip-enable. The 100-PQFP footprint is also pin-compatible across the entire MAX 7000S family, allowing future migration to larger macrocell counts (e.g., EPM7160SQC100) without PCB rework.
Recommended
Peripheral Control for 5V Microcontrollers
The EPM7128SQC100-10F is widely used as a peripheral controller for 5 V microcontrollers, providing glue logic, timers, and interface expansion in compact 5 V systems. The 84 user I/Os give the designer enough headroom to multiplex keypads, displays, sensors, and serial peripherals (UART, SPI, I2C glue) without external 74-series buffers. The 10 ns tPD ensures deterministic interrupt response and counter operation up to 100 MHz, useful for quadrature decoding or PWM generation. The CPLD is typically placed between the MCU and lower-speed peripherals, with JTAG programming handled by the same in-circuit debugger used for the MCU. This makes the EPM7128SQC100-10F a natural fit for industrial control, instrumentation front-ends, and HVAC controller boards that need 5 V logic and long production lifecycles.
Recommended
Legacy 74-Series TTL/CMOS Logic Replacement
The EPM7128SQC100-10F is a popular drop-in consolidation for legacy 74-series TTL and CMOS glue logic on mature industrial boards. The 128 macrocells and 84 I/Os can absorb several dozen discrete gates, muxes, latches, and flip-flops into a single in-system programmable device, reducing the 5 V power budget and freeing PCB area for higher-value analog and power components. Designers migrate discrete 74HC/74LS designs by capturing the original schematic in Verilog or VHDL, then reimplementing the same logic across 128 macrocells, and re-programming via JTAG without disturbing the existing 100-PQFP footprint. This approach is also used in long-lifecycle aerospace and military systems where 5 V supply rails are mandated and component obsolescence is a recurring supply-chain challenge.
Recommended
State-Machine and Sequencer Logic in Industrial Automation
The EPM7128SQC100-10F is well suited to state-machine and sequencer logic in industrial automation, where deterministic timing, non-volatile configuration, and 5 V I/O are required. The MAX 7000S architecture provides a uniform interconnect that routes state-machine outputs through a fast, predictable switch matrix, with 100 MHz counter speeds supporting high-rate sequencers for stepper-motor control or relay drivers. Designers typically implement the entire sequencer in VHDL and use the 84 I/Os to drive optocouplers, H-bridges, and indicator LEDs. The in-system programmable interface allows the same hardware to be re-tasked for different product variants by re-loading the JTAG image, accelerating production and field upgrades on the factory floor.
Recommended
Telecommunications Backplane Glue Logic
The EPM7128SQC100-10F is a workhorse in telecommunications backplane glue logic, where 5 V supply, deterministic timing, and reliable 84-I/O integration matter more than raw logic density. The 10 ns tPD and 100 MHz counter speed support E1/T1 framing, HDLC controllers, and bus arbitration between TDM switches on legacy backplanes. The EEPROM-based configuration ensures zero boot time on power-up, which is critical for hot-swap line cards that must be ready within milliseconds of insertion. The 100-PQFP package is footprint-compatible with the broader MAX 7000 family, allowing telecom OEMs to design one PCB that supports multiple macrocell sizes (EPM7064, EPM7128, EPM7160, EPM7256) by swapping a single chip. This makes the EPM7128SQC100-10F a long-standing choice for central-office and outside-plant equipment still in production today.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC100-10F β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC100-10 | EPM7128SQC100-10N | EPM7128EQC100-10 | EPM7128EQI100-15 | EPM7128BTC100-10 | EPM7128ATC100-10 |
|---|---|---|---|---|---|---|---|
| Package | PQFP-100 | PQFP-100 | PQFP-100 | PQFP-100 | PQFP-100 | PQFP-100 | PQFP-100 |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000E | MAX 7000E | MAX 7000B | MAX 7000A |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 15 ns | 10 ns | 10 ns |
| Counter Frequency | 100 MHz | 100 MHz | 100 MHz | 100 MHz | 76 MHz | 100 MHz | 100 MHz |
| Supply Voltage (VCCINT) | 5 V | 5 V | 5 V | 5 V | 5 V | 5 V | 3.3 V |
| Operating Temperature | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | -40C to +85C (industrial) | 0C to +70C | 0C to +70C |
| Lead-Free Finish | Yes (F suffix) | No | Yes (N suffix) | Yes | Yes | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Lead-free factory finish (F suffix) on a long-life 5 V CPLD (vs EPM7128SQC100-10)
- Industrial temperature grade option within the same footprint (vs EPM7128SQC100-10F)
- MAX 7000A family alternative for 3.3 V mixed-voltage designs (vs EPM7128ATC100-10)
Design Notes
The 100-pin PQFP package has a 0.65 mm pitch and a thermal pad ring; place a ground copper pour under the part and connect each GND pin (10, 20, 30, 40, 50, 60, 70, 90) directly to the pour to minimize ground bounce on high-speed outputs. Decoupling: place one 0.1 uF ceramic capacitor as close as possible to every VCC pin and one bulk 10 uF tantalum near the device. The JTAG chain (TDI/TDO/TMS/TCK) should be series-terminated with 33 ohm resistors if the JTAG cable length exceeds 15 cm to avoid reflection on the TCK edge.
A common pitfall is confusing the S, E, B, and A MAX 7000 sub-families. The EPM7128SQC100-10F is from the MAX 7000S family (5 V core only); the E variant is also 5 V but with enhanced interconnect; the A variant uses a 3.3 V core. Pin numbers and JTAG positions match across the 100-PQFP variants, but I/O standards and timing differ. If the design depends on a specific fMAX counter, double-check the datasheet counter specification for the chosen sub-family, because the A variant at 3.3 V may not meet the same fCNT as the 5 V S variant at 100 MHz.
When migrating a design from a non-F SnPb finish to the lead-free F finish, verify the reflow profile matches the JEDEC J-STD-020 peak of 260C. The 100-PQFP is a surface-mount package, and lead-free solder typically requires a higher soak time. Plan for an N-suffix or F-suffix verification before committing the assembly line to avoid tombstoning on the fine-pitch QFP leads.
The MAX 7000S I/O drivers have a fast edge rate (typically 1-2 ns) and can couple noise into adjacent traces; maintain at least 3W spacing between high-speed outputs and sensitive analog signals. Place a guard ground trace between CPLD outputs and analog sections. The 5 V I/O also requires a current-limiting series resistor (22-33 ohm) when driving long PCB traces (>10 cm) to reduce ringing on the rising edge.
Compliance Information
F suffix denotes lead-free (Pb-free) finish and RoHS compliance per distributor listings (DigiKey, Mouser) as of 2026-09-13. AEC-Q100 not applicable to commercial-grade CPLDs; industrial temperature variants (e.g., EPM7128EQI100-15) cover -40C to +85C.
