EPM7128SQC100-7 vs EPM7128SQC100-7N Comparison
Detailed side-by-side comparison of EPM7128SQC100-7 by Intel and EPM7128SQC100-7N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM7128SQC100-7 - 128-Macro 5V CPLD, 7.5ns, 100-Pin PQFP | Altera (Intel)
EPM7128SQC100-7 ObsoleteIntel
EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
EPM7128SQC100-7N ObsoleteSpecification Comparison
| Parameter | EPM7128SQC100-7 | EPM7128SQC100-7N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $10.85 | $7.10 |
| Product Type | CPLD - Complex Programmable Logic Device | β |
| Family | MAX 7000S | MAX 7000S |
| Macro Cells | 128 | β |
| Usable Gates | 2,500 | 2,500 |
| User I/Os | 84 | β |
| Logic Elements / LABs | 4 Logic Array Blocks (LABs) | β |
| Propagation Delay (tPD) | 7.5 ns | β |
| Maximum Internal Frequency | 125 MHz | β |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V | β |
| Technology | CMOS, EEPROM-based, non-volatile | β |
| Package | 100-pin PQFP (Plastic Quad Flat Pack) | 100-pin PQFP (QFP-100) |
| Programming Interface | JTAG (IEEE Std 1149.1), in-system programmable | β |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | 0C to +70C (commercial) |
| Mounting Type | Surface Mount | β |
| RoHS Status | Non-RoHS (legacy SnPb package) | Compliant (lead-free 'N' suffix) |
| Device Type | β | CPLD - Complex Programmable Logic Device |
| Program Memory Type | β | EEPROM |
| Number of Macrocells | β | 128 |
| Number of Logic Array Blocks | β | 8 |
| Number of Global Clocks | β | 2 |
| Product Terms per Macrocell | β | 32 |
| System Gates | β | 5,000 (max) |
| Maximum User I/Os | β | 84 |
| Pin-to-Pin Delay (tPD) | β | 7.5 ns |
| Counter Speed | β | 175.4 MHz |
| In-System Programmability | β | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | β | 5.0 V |
| I/O Standard Support | β | multiVolt (2.5V, 3.3V, 5.0V) |
| Process Technology | β | 0.30 Β΅m CMOS EEPROM |
| Security Bit | β | Programmable (one per device) |