EPM7128SQC100-7N - MAX 7000 CPLD, 128 Macrocells, 7.5ns, 100-Pin PQFP | Intel (Altera)
MPN: EPM7128SQC100-7N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $12.5 | $12.50 |
| 10 | $10.95 | $109.50 |
| 100 | $9.4 | $940.00 |
| 500 | $8.25 | $4,125.00 |
| 1,000 | $7.1 | $7,100.00 |
Drop-in alternatives for EPM7128SQC100-7N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM7128SQC100-7
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View Datasheet →EPM7128SQC100-10N
✅ Drop-In✓ In Stock
$14.95 / Unit
View Datasheet →EPM7128SQC100-10
✅ Drop-In✓ In Stock
$9.85 / Unit
View Datasheet →EPM7128AETC100-7N
✅ Drop-In✓ In Stock
$31.8 / Unit
View Datasheet →EPM7128AETC100-10
✅ Drop-In✓ In Stock
$13.85 / Unit
View Datasheet →ATF1508AS-7AU100
✅ Drop-In📋 Reference alternative (not in catalog)
EPM7128SQC100-7N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Device Type | CPLD - Complex Programmable Logic Device |
| Program Memory Type | EEPROM |
| Number of Macrocells | 128 |
| Number of Logic Array Blocks | 8 |
| Number of Global Clocks | 2 |
| Product Terms per Macrocell | 32 |
| Usable Gates | 2,500 |
| System Gates | 5,000 (max) |
| Maximum User I/Os | 84 |
| Pin-to-Pin Delay (tPD) | 7.5 ns |
| Counter Speed | 175.4 MHz |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Operating Voltage (Core) | 5.0 V |
| I/O Standard Support | multiVolt (2.5V, 3.3V, 5.0V) |
| Package | 100-pin PQFP (QFP-100) |
| Operating Temperature | 0C to +70C (commercial) |
| RoHS Status | Compliant (lead-free 'N' suffix) |
| Process Technology | 0.30 µm CMOS EEPROM |
| Security Bit | Programmable (one per device) |
EPM7128SQC100-7N Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | VCCINT — 5.0 V core supply |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | I/O — User I/O pin (bank 1) |
| Pin 16 | I/O — User I/O pin (bank 1) |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 1) |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | GND — Ground |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | I/O — User I/O pin (bank 2) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | I/O — User I/O pin (bank 2) |
| Pin 26 | I/O — User I/O pin (bank 2) |
| Pin 27 | I/O — User I/O pin (bank 2) |
| Pin 28 | I/O — User I/O pin (bank 2) |
| Pin 29 | I/O — User I/O pin (bank 2) |
| Pin 30 | I/O — User I/O pin (bank 2) |
| Pin 31 | VCCIO2 — I/O bank 2 supply (2.5/3.3/5V) |
| Pin 32 | I/O — User I/O pin (bank 2) |
| Pin 33 | I/O — User I/O pin (bank 2) |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | I/O — User I/O pin (bank 2) |
| Pin 37 | I/O — User I/O pin (bank 2) |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | I/O — User I/O pin (bank 2) |
| Pin 40 | GND — Ground |
| Pin 41 | TDI — JTAG Test Data In |
| Pin 42 | TMS — JTAG Test Mode Select |
| Pin 43 | TCK — JTAG Test Clock |
| Pin 44 | TDO — JTAG Test Data Out |
| Pin 45 | GND — Ground |
| Pin 46 | I/O — User I/O pin (bank 3) |
| Pin 47 | I/O — User I/O pin (bank 3) |
| Pin 48 | I/O — User I/O pin (bank 3) |
| Pin 49 | I/O — User I/O pin (bank 3) |
| Pin 50 | GCLK2 — Global clock input 2 |
| Pin 51 | GCLK1 — Global clock input 1 |
| Pin 52 | OE2/GCLK2 — Global clock 2 / output enable |
| Pin 53 | OE1/GCLK1 — Global clock 1 / output enable |
| Pin 54 | I/O — User I/O pin (bank 3) |
| Pin 55 | I/O — User I/O pin (bank 3) |
| Pin 56 | I/O — User I/O pin (bank 3) |
| Pin 57 | I/O — User I/O pin (bank 3) |
| Pin 58 | I/O — User I/O pin (bank 3) |
| Pin 59 | VCCIO3 — I/O bank 3 supply (2.5/3.3/5V) |
| Pin 60 | I/O — User I/O pin (bank 3) |
| Pin 61 | I/O — User I/O pin (bank 3) |
| Pin 62 | I/O — User I/O pin (bank 3) |
| Pin 63 | I/O — User I/O pin (bank 3) |
| Pin 64 | I/O — User I/O pin (bank 3) |
| Pin 65 | GND — Ground |
| Pin 66 | I/O — User I/O pin (bank 4) |
| Pin 67 | I/O — User I/O pin (bank 4) |
| Pin 68 | I/O — User I/O pin (bank 4) |
| Pin 69 | I/O — User I/O pin (bank 4) |
| Pin 70 | I/O — User I/O pin (bank 4) |
| Pin 71 | I/O — User I/O pin (bank 4) |
| Pin 72 | I/O — User I/O pin (bank 4) |
| Pin 73 | I/O — User I/O pin (bank 4) |
| Pin 74 | I/O — User I/O pin (bank 4) |
| Pin 75 | VCCIO4 — I/O bank 4 supply (2.5/3.3/5V) |
| Pin 76 | I/O — User I/O pin (bank 4) |
| Pin 77 | I/O — User I/O pin (bank 4) |
| Pin 78 | I/O — User I/O pin (bank 4) |
| Pin 79 | I/O — User I/O pin (bank 4) |
| Pin 80 | I/O — User I/O pin (bank 4) |
| Pin 81 | I/O — User I/O pin (bank 4) |
| Pin 82 | I/O — User I/O pin (bank 4) |
| Pin 83 | I/O — User I/O pin (bank 4) |
| Pin 84 | I/O — User I/O pin (bank 4) |
| Pin 85 | GND — Ground |
| Pin 86 | I/O — User I/O pin (bank 5) |
| Pin 87 | I/O — User I/O pin (bank 5) |
| Pin 88 | I/O — User I/O pin (bank 5) |
| Pin 89 | I/O — User I/O pin (bank 5) |
| Pin 90 | I/O — User I/O pin (bank 5) |
| Pin 91 | I/O — User I/O pin (bank 5) |
| Pin 92 | I/O — User I/O pin (bank 5) |
| Pin 93 | I/O — User I/O pin (bank 5) |
| Pin 94 | I/O — User I/O pin (bank 5) |
| Pin 95 | I/O — User I/O pin (bank 5) |
| Pin 96 | VCCIO5 — I/O bank 5 supply (2.5/3.3/5V) |
| Pin 97 | I/O — User I/O pin (bank 5) |
| Pin 98 | I/O — User I/O pin (bank 5) |
| Pin 99 | I/O — User I/O pin (bank 5) |
| Pin 100 | GND — Ground |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128SQC100-7N is suitable for 6 applications: Legacy Industrial Glue Logic, Address Decoding & Bus Arbitration, Peripheral I/O Expansion, State Machine & Protocol Bridging, Telecom & Networking Line Cards, Test & Measurement Equipment.
Legacy Industrial Glue Logic
The EPM7128SQC100-7N is widely deployed in legacy industrial glue logic, where it replaces dozens of discrete 74LS/74HC TTL gates with a single programmable device. Its 128 macrocells and 84 user I/Os handle address decoding, bus multiplexing, chip-select generation, and interrupt steering in PLC racks, motor-control boards, and factory automation equipment. The 5V core with multiVolt I/O allows direct interface to both 5V legacy bus transceivers and 3.3V microcontrollers without external level shifters, simplifying PCB routing. Instant-on behavior from EEPROM configuration eliminates boot delay, critical in deterministic real-time control loops. Engineers maintaining installed-base CNC machines, SCADA systems, and programmable logic controllers find the -7N variant indispensable.
Recommended
Address Decoding & Bus Arbitration
In microcontroller and microprocessor systems, the EPM7128SQC100-7N excels at address decoding, chip-select generation, and bus arbitration between multiple masters. Its 7.5 ns pin-to-pin delay is fast enough to interpose between a CPU and memory peripherals without adding wait states. The 32 product terms per macrocell allow complex Boolean expressions for window decoding in memory-mapped systems. Banks of I/O can be assigned to different voltage domains, supporting mixed 5V/3.3V/2.5V systems. JTAG-based in-system programmability enables firmware engineers to update glue logic in the field without removing the device from the board, a major benefit for industrial embedded systems.
Recommended
Peripheral I/O Expansion
The EPM7128SQC100-7N is frequently used to expand I/O count in microcontroller-based designs where the MCU has insufficient pins. With 84 user I/Os and individually configurable I/O standards (2.5V, 3.3V, 5.0V), the CPLD acts as a flexible I/O extender that offloads real-time I/O toggling from software. Applications include keypad scanning, seven-segment display multiplexing, parallel port emulation (Centronics), and motor-driver interface logic. The -7 speed grade sustains 175.4 MHz counter frequencies, suitable for high-speed pulse generation, quadrature decoding, and PWM peripherals. EEPROM configuration means no external boot PROM is needed.
Recommended
State Machine & Protocol Bridging
The EPM7128SQC100-7N is a classic platform for implementing complex state machines and protocol-bridging logic. With 128 macrocells and abundant product terms, designers can implement UART, SPI, I2C, and custom bit-banging protocol converters. Its 7.5 ns tPD enables reliable operation up to ~60 MHz, covering most legacy serial protocols. MultiVolt I/O allows bridging between 5V legacy buses and 3.3V modern ASICs without glue logic. Use cases include legacy mainframe interface boards, medical device controllers, and aerospace test fixtures where deterministic state-machine behavior is mandatory. The non-volatile EEPROM configuration means power-on behavior is predictable and identical across resets.
Recommended
Telecom & Networking Line Cards
In telecom and networking equipment, the EPM7128SQC100-7N is used on T1/E1, TDM, and legacy ATM line-interface cards for time-slot assignment, clock distribution, and protocol framing. The 2 global clocks with complementary inputs support primary and backup clock trees with glitch-free switching. 5V-tolerant I/O interfaces directly with ECL/TTL line-interface units, while the JTAG ISP allows board-level diagnostics. Counter speeds up to 175.4 MHz enable bit-rate generation for sub-2.5G serial protocols. Although obsolete for new builds, the -7N variant remains in service for legacy SONET/SDH and cross-connect equipment that requires decade-long field support.
Recommended
Test & Measurement Equipment
The EPM7128SQC100-7N finds application in bench-top and rack-mount test equipment, including logic analyzers, pattern generators, and ATE (Automated Test Equipment) interface boards. Its deterministic 7.5 ns timing supports stimulus generation with precise edge placement, while 128 macrocells hold substantial pattern sequences. MultiVolt I/O is essential for interfacing to DUTs (devices-under-test) at any voltage from 1.8V to 5V. ISP via JTAG enables field calibration updates. The 100-pin PQFP package is easily socketed for engineering builds. Long product lifecycles of test platforms mean the EPM7128SQC100-7N continues to be specified even as new CPLD designs migrate to MAX II/MAX V families.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128SQC100-7N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128SQC100-7 | EPM7128SQC100-10N | EPM7128SQC100-10 | EPM7128AETC100-7N | EPM7128AETC100-10 | ATF1508AS-7AU100 |
|---|---|---|---|---|---|---|---|
| Package | QFP-100 | QFP-100 - same | QFP-100 - same | QFP-100 - same | QFP-100 - same | QFP-100 - same | TQFP-100 - same footprint |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Microchip Technology |
| Pin-to-Pin Delay (tPD) | 7.5 ns | 7.5 ns | 10 ns | 10 ns | 7 ns | 10 ns | 7 ns |
| Macrocells | 128 | 128 | 128 | 128 | 128 | 128 | 128 |
| Maximum User I/Os | 84 | 84 | 84 | 84 | 84 | 84 | 100 |
| Counter Speed | 175.4 MHz | 175.4 MHz | 125 MHz | 125 MHz | 200 MHz | 125 MHz | 200 MHz |
| Core Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 3.3 V | 3.3 V | 5.0 V |
| RoHS / Lead-Free | Yes (Pb-free) | No (SnPb) | Yes (Pb-free) | No (SnPb) | Yes (Pb-free) | No (SnPb) | Yes (Pb-free) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Active |
Key Differentiators
- Active drop-in replacement available with full IP migration tooling (vs ATF1508AS-7AU100)
- Identical silicon, free RoHS upgrade for new designs (vs EPM7128SQC100-7)
- Higher counter speed than slower speed-grade siblings (vs EPM7128SQC100-10N)
Design Notes
The EPM7128SQC100-7N requires a clean 5.0V ±5% supply on VCCINT (pin 9) and separate VCCIO bank supplies (VCCIO2 at pin 31, VCCIO3 at pin 59, VCCIO4 at pin 75, VCCIO5 at pin 96) for multiVolt I/O. Decouple each supply pin with a 0.1µF ceramic capacitor placed within 5mm of the pin, and add a bulk 10µF tantalum capacitor at the board entry. The ICCINT current peaks during programming and at high toggle rates; budget 200mA peak ICCINT plus per-bank I/O current. Power sequencing: VCCINT must rise monotonically and reach 4.5V before any logic operation; during power-down, all VCC supplies must remain above 2.7V to avoid I/O latch-up.
The 100-pin PQFP package has 0.65mm pitch leads. Per IPC-7351 guidelines, use 0.4mm-wide copper pads with 0.15mm solder mask expansion. Provide at least 4 vias under the die pad (none on this PQFP - it has no thermal pad) and flood top/bottom ground planes for return paths. Route JTAG signals (TDI/TMS/TCK/TDO on pins 41-44) with 50Ω controlled impedance to avoid boundary-scan failures at 10MHz TCK. Isolate JTAG chain from high-speed edge signals to prevent crosstalk. Add a 4.7kΩ pull-up on TMS and TDI to keep the TAP controller in Test-Logic-Reset when unused.
Three pitfalls to avoid with the EPM7128SQC100-7N: (1) Do not confuse 'SQC' (PQFP) with 'STC' (TQFP) or 'SLC' (PLCC) - same die, different package footprints are not pin-compatible. (2) The -7, -10, and -15 speed grades are NOT drop-in interchangeable in timing-sensitive paths because tPD scales from 7.5ns to 15ns. (3) The non-N ('-7' without 'N') variant uses tin-lead finish and is NOT RoHS compliant - import to EU markets will fail. Always verify the full ordering code with Intel/Altera's ordering information decoder before procurement.
Place the EPM7128SQC100-7N within 25mm of its supporting components to minimize stub lengths. Use a star-ground topology from a single ground reference point at the regulator return. Maintain 3W spacing between JTAG signals and adjacent high-current traces to prevent noise coupling during ISP. Reserve a contiguous PCB area (~20mm x 20mm) for socket compatibility if engineering builds require device removal. For production, allocate a board-programming header footprint for JTAG ISP via ByteBlaster or USB-Blaster download cables.
Compliance Information
Per Arrow's EPM7128SQC100-7N listing: EU RoHS Compliant, ECCN EAR99, SVHC flagged as Yes. The -N suffix confirms Pb-free matte-tin finish. Halogen-free status not specified in the provided data. AEC-Q100 not applicable for this industrial-grade CPLD.
