EPM7128STC100-10N vs EPM7128STI100-10N Comparison
Detailed side-by-side comparison of EPM7128STC100-10N by Altera and EPM7128STI100-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
EPM7128STC100-10N NrndAltera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoleteSpecification Comparison
| Parameter | EPM7128STC100-10N | EPM7128STI100-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 7000S | MAX 7000S |
| Product Type | CPLD - Complex Programmable Logic Device | — |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 | 2,500 (up to 5,000 family max) |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) | 8 |
| User I/Os | 84 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Internal Frequency (fMAX) | 100 MHz | — |
| Supply Voltage (VCCINT) | 5 V | — |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) | — |
| Process Technology | CMOS EEPROM | — |
| Package | 100-pin TQFP (14 x 14 x 1 mm) | 100-pin TQFP |
| Operating Temperature | 0 C to +70 C (commercial) | -40C to +85C (Industrial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (JTAG IEEE 1149.1) |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | Compliant (Pb-free "N" suffix) | [DATA_NEEDED: RoHS status] |
| Lead-Free | Yes | — |
| Architecture | — | CMOS EEPROM-based CPLD |
| Maximum User I/O | — | 84 |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Counter Frequency | — | 175.4 MHz |
| Supply Voltage (VCC) | — | 5 V |
| JTAG Boundary-Scan | — | Yes (BST) |
| MSL Level | — | [DATA_NEEDED: MSL level] |
| Open-Drain I/O Option | — | Available (per MAX 7000A feature set) |