EPM7128STC100-10N - MAX 7000S CPLD 128-Macrocell 10ns TQFP-100 | Altera
MPN: EPM7128STC100-10N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $14.5 | $14.50 |
| 10 | $13.05 | $130.50 |
| 100 | $11.6 | $1,160.00 |
| 500 | $10.45 | $5,225.00 |
| 1,000 | $9.3 | $9,300.00 |
Drop-in alternatives for EPM7128STC100-10N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM7128STC100-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 7000S |
| Product Type | CPLD - Complex Programmable Logic Device |
| Macrocells | 128 |
| Usable Gates | 2,500 |
| Logic Array Blocks (LABs) | 8 (16 macrocells each) |
| User I/Os | 84 |
| Propagation Delay (tPD) | 10 ns |
| Internal Frequency (fMAX) | 100 MHz |
| Supply Voltage (VCCINT) | 5 V |
| I/O Voltage (VCCIO) | 3.3 V or 5 V (MultiVolt) |
| Process Technology | CMOS EEPROM |
| Package | 100-pin TQFP (14 x 14 x 1 mm) |
| Operating Temperature | 0 C to +70 C (commercial) |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Mounting Type | Surface Mount |
| RoHS Status | Compliant (Pb-free "N" suffix) |
| Lead-Free | Yes |
EPM7128STC100-10N Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | VCCINT — 5V core supply |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | I/O — User I/O pin (bank 1) |
| Pin 13 | I/O — User I/O pin (bank 1) |
| Pin 14 | I/O — User I/O pin (bank 1) |
| Pin 15 | I/O — User I/O pin (bank 1) |
| Pin 16 | GND — Ground |
| Pin 17 | I/O — User I/O pin (bank 1) |
| Pin 18 | I/O — User I/O pin (bank 1) |
| Pin 19 | I/O — User I/O pin (bank 1) |
| Pin 20 | I/O — User I/O pin (bank 1) |
| Pin 21 | I/O — User I/O pin (bank 1) |
| Pin 22 | I/O — User I/O pin (bank 1) |
| Pin 23 | I/O — User I/O pin (bank 1) |
| Pin 24 | GND — Ground |
| Pin 25 | I/O — User I/O pin (bank 1) |
| Pin 26 | I/O — User I/O pin (bank 1) |
| Pin 27 | I/O — User I/O pin (bank 1) |
| Pin 28 | I/O — User I/O pin (bank 1) |
| Pin 29 | I/O — User I/O pin (bank 1) |
| Pin 30 | I/O — User I/O pin (bank 1) |
| Pin 31 | I/O — User I/O pin (bank 1) |
| Pin 32 | VCCIO — I/O supply (3.3V or 5V) |
| Pin 33 | I/O — User I/O pin (bank 2) |
| Pin 34 | I/O — User I/O pin (bank 2) |
| Pin 35 | I/O — User I/O pin (bank 2) |
| Pin 36 | I/O — User I/O pin (bank 2) |
| Pin 37 | I/O — User I/O pin (bank 2) |
| Pin 38 | I/O — User I/O pin (bank 2) |
| Pin 39 | I/O — User I/O pin (bank 2) |
| Pin 40 | GND — Ground |
| Pin 41 | I/O — User I/O pin (bank 2) |
| Pin 42 | I/O — User I/O pin (bank 2) |
| Pin 43 | I/O — User I/O pin (bank 2) |
| Pin 44 | I/O — User I/O pin (bank 2) |
| Pin 45 | I/O — User I/O pin (bank 2) |
| Pin 46 | I/O — User I/O pin (bank 2) |
| Pin 47 | I/O — User I/O pin (bank 2) |
| Pin 48 | GND — Ground |
| Pin 49 | I/O — User I/O pin (bank 2) |
| Pin 50 | I/O — User I/O pin (bank 2) |
| Pin 51 | I/O — User I/O pin (bank 2) |
| Pin 52 | I/O — User I/O pin (bank 2) |
| Pin 53 | I/O — User I/O pin (bank 2) |
| Pin 54 | I/O — User I/O pin (bank 2) |
| Pin 55 | I/O — User I/O pin (bank 2) |
| Pin 56 | VCCINT — 5V core supply |
| Pin 57 | I/O — User I/O pin (bank 2) |
| Pin 58 | I/O — User I/O pin (bank 2) |
| Pin 59 | I/O — User I/O pin (bank 2) |
| Pin 60 | I/O — User I/O pin (bank 2) |
| Pin 61 | I/O — User I/O pin (bank 2) |
| Pin 62 | I/O — User I/O pin (bank 2) |
| Pin 63 | I/O — User I/O pin (bank 2) |
| Pin 64 | GND — Ground |
| Pin 65 | I/O — User I/O pin (bank 2) |
| Pin 66 | I/O — User I/O pin (bank 2) |
| Pin 67 | I/O — User I/O pin (bank 2) |
| Pin 68 | I/O — User I/O pin (bank 2) |
| Pin 69 | I/O — User I/O pin (bank 2) |
| Pin 70 | I/O — User I/O pin (bank 2) |
| Pin 71 | I/O — User I/O pin (bank 2) |
| Pin 72 | VCCIO — I/O supply (3.3V or 5V) |
| Pin 73 | I/O — User I/O pin (bank 2) |
| Pin 74 | I/O — User I/O pin (bank 2) |
| Pin 75 | I/O — User I/O pin (bank 2) |
| Pin 76 | I/O — User I/O pin (bank 2) |
| Pin 77 | I/O — User I/O pin (bank 2) |
| Pin 78 | I/O — User I/O pin (bank 2) |
| Pin 79 | I/O — User I/O pin (bank 2) |
| Pin 80 | GND — Ground |
| Pin 81 | I/O — User I/O pin (bank 2) |
| Pin 82 | I/O — User I/O pin (bank 2) |
| Pin 83 | I/O — User I/O pin (bank 2) |
| Pin 84 | I/O — User I/O pin (bank 2) |
| Pin 85 | TDI — JTAG Test Data In |
| Pin 86 | TMS — JTAG Test Mode Select |
| Pin 87 | TCK — JTAG Test Clock |
| Pin 88 | VCCINT — 5V core supply |
| Pin 89 | I/O — User I/O pin (bank 2) |
| Pin 90 | I/O — User I/O pin (bank 2) |
| Pin 91 | I/O — User I/O pin (bank 2) |
| Pin 92 | I/O — User I/O pin (bank 2) |
| Pin 93 | I/O — User I/O pin (bank 2) |
| Pin 94 | I/O — User I/O pin (bank 2) |
| Pin 95 | I/O — User I/O pin (bank 2) |
| Pin 96 | GND — Ground |
| Pin 97 | I/O — User I/O pin (bank 1) |
| Pin 98 | I/O — User I/O pin (bank 1) |
| Pin 99 | I/O — User I/O pin (bank 1) |
| Pin 100 | TDO — JTAG Test Data Out |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7128STC100-10N is suitable for 7 applications: PCI-to-ISA Bus Bridge, Microcontroller Glue Logic, Industrial Control State Machines, Communication Protocol Converter, Power Supply Sequencing Logic, Address Decoding and Chip-Select Generation, Legacy 74-Series Logic Replacement.
PCI-to-ISA Bus Bridge
The EPM7128STC100-10N is well-suited as a PCI-to-ISA bus bridge controller because its 84 user I/Os can accommodate the 49 PCI signals plus 53 ISA signals after de-multiplexing, while its 10 ns tPD easily meets the 33 MHz PCI clock-to-out timing (tVAL 11 ns max). The 128 macrocells provide ample capacity for address decoding, command decoding, and interrupt steering logic between the two buses. Non-volatile EEPROM-based configuration ensures the bridge is active at power-on with no boot delay, critical for system BIOS hand-off during POST. MultiVolt I/O allows the 5V PCI signals and 5V ISA bus to share the same device with no external level shifters, reducing BOM cost and board area.
Recommended
Microcontroller Glue Logic
Use the EPM7128STC100-10N to consolidate discrete 74-series glue logic around a microcontroller, replacing 5-15 individual 74HC/74AHC packages with a single programmable device. The 128 macrocells and 84 I/Os provide generous capacity for address latch generation, chip-select decoding, interrupt encoding, wait-state insertion, and bus multiplexing between an 8-bit or 16-bit MCU and external peripherals. The 10 ns propagation delay ensures the CPLD does not become the limiting factor in the timing budget for buses up to 50 MHz, and JTAG-based in-system programmability allows last-minute pin reassignment without PCB rework.
Recommended
Industrial Control State Machines
Deploy the EPM7128STC100-10N as a deterministic state-machine controller for industrial automation lines, where its non-volatile configuration and instant-on behavior eliminate the boot-time uncertainty of FPGAs or processor-based controllers. The 128 macrocells support Mealy or Moore machines with up to 16-20 states plus output combinational logic, while 84 I/Os can drive sensor inputs, solenoid drivers, and HMI displays simultaneously. The commercial 0-70C temperature range suits factory-floor enclosures, and the JTAG interface enables on-line reprogramming for firmware updates without removing the PCB from the control cabinet. Hardened against single-event upset compared to SRAM-based logic, the EEPROM cells are immune to voltage glitches during power sequencing.
Recommended
Communication Protocol Converter
Implement UART-to-SPI, SPI-to-I2C, or RS-232-to-RS-485 protocol converters using the EPM7128STC100-10N, leveraging its bidirectional I/O cells to interface both sides of the conversion without external transceivers. The 128 macrocells fit a complete UART (start/stop bit handling, baud-rate generator, FIFO-like state machine) plus an SPI master/slave controller in a single device, while the 10 ns tPD supports SPI clock rates up to 50 MHz. MultiVolt I/O allows the converter to bridge 5V legacy UART lines with 3.3V modern MCUs directly, eliminating level-shifters in mixed-voltage designs.
Recommended
Power Supply Sequencing Logic
Use the EPM7128STC100-10N to sequence multiple power rails in a complex system (e.g., 1.2V core, 1.8V DDR, 3.3V I/O, 5V analog) by monitoring PG (Power Good) signals and asserting enable pins in the correct order with programmable delay. The 128 macrocells support a sequencing engine handling 8-16 rails with adjustable rise times, while the 84 I/Os provide PG inputs plus EN outputs plus status LEDs. The 5V-tolerant inputs interface directly with most supervisor ICs, and the deterministic 10 ns delay enables precise rail-to-rail timing alignment. The non-volatile configuration preserves the sequencing program through power cycles and brown-out events.
Recommended
Address Decoding and Chip-Select Generation
Generate chip-select signals for memory banks, peripheral devices, and I/O expanders from a single EPM7128STC100-10N, replacing 4-8 discrete 74HC138/74HC139 decoders with one programmable device. The 128 macrocells implement 16-32 independent chip-select decoders with programmable address ranges, chip-enable polarity, and output drive characteristics. With 10 ns tPD, the chip-select signals arrive within one clock cycle of address valid, supporting microprocessors and microcontrollers up to 50 MHz without wait-state insertion. JTAG in-system programming allows design changes to the memory map without PCB rework.
Recommended
Legacy 74-Series Logic Replacement
Replace obsolete or hard-to-source 74LS/74HC/74F-series discrete logic packages with a single EPM7128STC100-10N, consolidating what would otherwise require 8-15 DIP/SOIC packages into one TQFP-100 surface-mount device. This dramatically reduces PCB area, eliminates multi-vendor sourcing issues for legacy logic, and provides documented timing via the CPLD's datasheet instead of relying on per-family timing parameters. The 84 user I/Os map directly to standard 74-series pin groupings, and JTAG programming lets you re-implement the logic as design needs evolve without respinning the PCB.
Recommended
Recommended Products Summary
Engineering reference data for EPM7128STC100-10N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7128STC100-10 | EPM7128STC100-15N | EPM7128AETC100-10N | EPM7128AETC100-7N |
|---|---|---|---|---|---|
| Package | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 | TQFP-100 |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Family | MAX 7000S | MAX 7000S | MAX 7000S | MAX 7000AE | MAX 7000AE |
| Macrocells | 128 | 128 | 128 | 128 | 128 |
| User I/Os | 84 | 84 | 84 | 84 | 84 |
| Propagation Delay (tPD) | 10 ns | 10 ns | 15 ns | 12.5 ns | 7.5 ns |
| Internal Frequency (fMAX) | 100 MHz | 100 MHz | 76 MHz | 90 MHz | 125 MHz |
| VCCIO Support | 3.3V / 5V | 3.3V / 5V | 3.3V / 5V | 2.5V / 3.3V / 5V | 2.5V / 3.3V / 5V |
| Lead-Free | Yes (Pb-free N suffix) | No (SnPb finish) | Yes (Pb-free N suffix) | Yes (Pb-free N suffix) | Yes (Pb-free N suffix) |
| Lifecycle | NRND | NRND | NRND | Active | Active |
Key Differentiators
- Lead-free Pb-free terminal finish (RoHS compliant) (vs EPM7128STC100-10 (non-N variant))
- 10 ns speed grade vs 15 ns alternative (vs EPM7128STC100-15N)
- Original MAX 7000S architecture with MultiVolt I/O (vs EPM7128AETC100-10N (MAX 7000AE))
- 100-pin TQFP surface-mount footprint (vs EPM7128SLC84-10 (PLCC-84))
Design Notes
Decouple VCCINT (5V) and VCCIO (3.3V or 5V) separately with one 0.1 µF ceramic capacitor within 3 mm of each power pin, plus a 10 µF bulk tantalum or ceramic capacitor near the device. The MAX 7000S family draws approximately 50-150 mA ICCINT at 100 MHz depending on utilization; use a regulator with at least 250 mA headroom. VCCIO must be stable before or simultaneously with VCCINT to prevent latch-up - sequence with a supervisor or use a common rail with adequate RC delay. Estimated: Icc scales linearly with fMAX and approximately quadratically with toggle rate; measure in-circuit to verify.
Route JTAG signals (TDI, TMS, TCK, TDO) as a daisy-chain with 10 kΩ pull-up on TCK and TMS, and 10 kΩ pull-up on TDI per IEEE 1149.1. Keep JTAG traces under 150 mm and away from clock signals. The TQFP-100 has a 0.5 mm pitch - use 0.15 mm trace/space design rules and micro-vias if HDI is available. Exposed-pad variants are not used on this package; standard 100-pin TQFP does not require a thermal pad.
Configure VCCIO bank-by-bank to match the I/O voltage of the connected bus (3.3V or 5V); mixing voltages within a single bank is not supported. Unused I/O pins should be configured as outputs driving low or as inputs with internal pull-ups enabled to avoid floating-pin Icc drift. For high-speed outputs (>50 MHz), use a series damping resistor (22-33 ohm) close to the CPLD pin to dampen transmission-line ringing on long traces.
Do not apply JTAG signals before VCCINT and VCCIO have stabilized, or the device may enter an undefined state. The MAX 7000S is 5V-tolerant on inputs but VCCIO must be present for the I/O cells to function correctly. Do not assume compatibility with MAX 3000A or MAX II pinouts - they are different packages with different power pins. When migrating from non-N to N suffix, verify the reflow profile (peak 260C for N variant vs 240C for SnPb) - high peak temperatures may damage the Pb-free matte-tin finish or warp the TQFP body.
Compliance Information
RoHS compliant per "N" suffix designating Pb-free matte-tin finish. Not AEC-Q100 qualified (industrial/commercial grade only). Halogen-free status not explicitly stated in available data - marked unknown.
