EPM7160EQC160-12 vs EPM7160SQC160-6 Comparison

Detailed side-by-side comparison of EPM7160EQC160-12 by Intel and EPM7160SQC160-6 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7160EQC160-12 EPM7160SQC160-6
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Active Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $9.75 $5.45
Family MAX 7000E β€”
Macrocells 160 β€”
Logic Array Blocks (LABs) 4 β€”
Usable Gates 3,200 β€”
User I/O Pins 104 β€”
Pin-to-Pin Logic Delay (tPD) 12 ns β€”
Supply Voltage (VCCINT) 5.0 V 4.75 V to 5.25 V (nominal 5 V)
I/O Voltage 5.0 V β€”
In-System Programmability Yes (JTAG IEEE 1149.1) β€”
Non-volatile Configuration EEPROM β€”
Global Clocks 4 β€”
Operating Temperature 0 Β°C to +70 Β°C (Commercial) 0 C to 70 C (commercial)
Package PQFP-160 (EQC), Gull-Wing 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] β€”
MSL Level [DATA_NEEDED: MSL level] β€”
Series β€” MAX 7000S
Product Type β€” CPLD (Complex Programmable Logic Device)
Programmable Type β€” In System Programmable (ISP), EEPROM-based
Number of Macrocells β€” 160
Number of Logic Elements/Blocks β€” 10 LABs (Logic Array Blocks)
Number of Usable Gates β€” 3,200
Number of I/O Pins β€” 104
Propagation Delay (tpd) β€” 6 ns (max, pin-to-pin)
Maximum Internal Frequency β€” 167 MHz
Logic Family β€” CMOS, TTL-compatible I/O
Program/Erase Endurance β€” 100 cycles (EEPROM)
JTAG / Boundary Scan β€” IEEE Std 1149.1 compliant
Dedicated Input Pins β€” 4 (GCLK1, GCLRn, OE1, OE2/GCLK2)

Datasheets & Resources

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