EPM7160EQC160-12 vs EPM7160SQC160-6 Comparaison
Comparaison détaillée côte à côte de EPM7160EQC160-12 par Intel et EPM7160SQC160-6 par Altera. Comparez les spécifications clés, les paramètres électriques, le conditionnement, le statut de cycle de vie, les prix et la disponibilité pour déterminer le meilleur composant pour vos exigences de conception.
Altera
EPM7160SQC160-6 - 160-Macrocell MAX 7000S CPLD, 6ns, PQFP-160 | Altera
EPM7160SQC160-6 ObsoleteComparaison des spécifications
| Paramètre | EPM7160EQC160-12 | EPM7160SQC160-6 |
|---|---|---|
| Marque | Intel | Altera |
| Catégorie | FPGA & CPLD | FPGA & CPLD |
| Statut du cycle de vie | Actif | Obsolete |
| Statut du stock | In Stock | In Stock |
| Prix unitaire (USD) | $9,75 | $5,45 |
| Family | MAX 7000E | — |
| Macrocells | 160 | — |
| Logic Array Blocks (LABs) | 4 | — |
| Usable Gates | 3,200 | — |
| User I/O Pins | 104 | — |
| Pin-to-Pin Logic Delay (tPD) | 12 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | 4.75 V to 5.25 V (nominal 5 V) |
| I/O Voltage | 5.0 V | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | — |
| Non-volatile Configuration | EEPROM | — |
| Global Clocks | 4 | — |
| Température de fonctionnement | 0 °C to +70 °C (Commercial) | 0 C to 70 C (commercial) |
| Boîtier | PQFP-160 (EQC), Gull-Wing | 160-pin PQFP (Plastic Quad Flat Pack), 28x28 mm body |
| Type de montage | Surface Mount | Surface Mount |
| Statut RoHS | [DATA_NEEDED: RoHS status] | — |
| Niveau MSL | [DATA_NEEDED: MSL level] | — |
| Series | — | MAX 7000S |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Programmable Type | — | In System Programmable (ISP), EEPROM-based |
| Number of Macrocells | — | 160 |
| Number of Logic Elements/Blocks | — | 10 LABs (Logic Array Blocks) |
| Number of Usable Gates | — | 3,200 |
| Number of I/O Pins | — | 104 |
| Propagation Delay (tpd) | — | 6 ns (max, pin-to-pin) |
| Maximum Internal Frequency | — | 167 MHz |
| Logic Family | — | CMOS, TTL-compatible I/O |
| Program/Erase Endurance | — | 100 cycles (EEPROM) |
| JTAG / Boundary Scan | — | IEEE Std 1149.1 compliant |
| Dedicated Input Pins | — | 4 (GCLK1, GCLRn, OE1, OE2/GCLK2) |