EPM7160SQC160-10 vs EPM7192SQC160-15 Comparison
Detailed side-by-side comparison of EPM7160SQC160-10 by Altera and EPM7192SQC160-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7160SQC160-10 - MAX 7000S CPLD, 160 Macro Cells, 100MHz, PQFP-160 | Intel / Altera
EPM7160SQC160-10 ObsoleteSpecification Comparison
| Parameter | EPM7160SQC160-10 | EPM7192SQC160-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000S |
| Macro Cells | 160 | — |
| Logic Elements / Gates | 3,200 usable gates | — |
| User I/Os | 104 | — |
| Logic Array Blocks (LABs) | 10 | — |
| Maximum Operating Frequency | 100 MHz | 76.9 MHz |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Voltage Tolerance | 5.0 V | — |
| Programming Technology | EEPROM, in-system programmable | — |
| JTAG Support | IEEE 1149.1 (boundary-scan + ISP) | — |
| Package | PQFP-160 (SQC160) | PQFP-160 |
| Operating Temperature | 0 C to +70 C (commercial) | — |
| Logic Family | CMOS | — |
| Mounting Type | Surface Mount | Surface Mount |
| Process Technology | CMOS, EEPROM-based | CMOS, EEPROM-based |
| RoHS Status | unknown | — |
| Lead-Free | unknown | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Supply Voltage | — | 5.0 V |
| Programmability | — | In-System (ISP) via JTAG IEEE Std 1149.1 |
| Configuration Memory | — | EEPROM, non-volatile |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |