EPM7192EGM160-20 vs EPM7192SQC160-10 Comparison
Detailed side-by-side comparison of EPM7192EGM160-20 by Altera and EPM7192SQC160-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192EGM160-20 - 192-Macrocell MAX 7000 CPLD, 20ns PGA-160 | Altera
EPM7192EGM160-20 ObsoleteAltera
EPM7192SQC160-10 - 192-Macro MAX 7000S CPLD, 100MHz, PQFP-160 | Intel / Altera
EPM7192SQC160-10 NrndSpecification Comparison
| Parameter | EPM7192EGM160-20 | EPM7192SQC160-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000 | MAX 7000S |
| Device Type | EE CMOS CPLD (Electrically Erasable) | — |
| Macrocells | 192 | 192 |
| Logic Array Blocks (LABs) | 12 | 4 |
| Usable Gates | 600 to 5,000 | 3750 |
| Maximum User I/O Pins | 120 | — |
| Package | PGA-160 (160-pin Pin Grid Array) | PQFP-160 (SQC) 28x28 mm |
| Speed Grade | -20 (20 ns pin-to-pin) | — |
| Pin-to-Pin Propagation Delay | 20 ns | — |
| Counter Frequency (max) | 175.4 MHz | — |
| I/O Standards | 3.3 V or 5 V configurable | — |
| Global Clock Inputs | 2 (GCLK1, GCLK2) | — |
| In-System Programming | Yes (JTAG IEEE 1149.1) | — |
| Program/Erase Endurance | 100 cycles (EEPROM) | — |
| Operating Temperature | -40C to +125C (industrial) | — |
| Technology Node | CMOS, second-generation MAX architecture | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| User I/Os | — | 124 |
| Propagation Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Supply Voltage (VCCINT) | — | 5.0 V |
| Program Memory Type | — | EEPROM |
| In-System Programmability | — | Yes (JTAG IEEE 1149.1) |
| Pin/Package Type | — | Surface Mount, Gull-Wing |
| Operating Temperature (Commercial) | — | 0C to +70C |
| Lead Finish | — | [DATA_NEEDED: lead finish] |