EPM7192SQC160-7N vs EPM7192SQC160-10N Comparison
Detailed side-by-side comparison of EPM7192SQC160-7N by Altera and EPM7192SQC160-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM7192SQC160-7N - MAX 7000S 192-Macro CPLD, 7.5ns, PQFP-160 | Altera
EPM7192SQC160-7N ObsoleteAltera
EPM7192SQC160-10N - 192-Macrocell MAX 7000S CPLD, 10ns, 160-Pin PQFP | Altera
EPM7192SQC160-10N NrndSpecification Comparison
| Parameter | EPM7192SQC160-7N | EPM7192SQC160-10N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 7000S | MAX 7000 |
| Logic Family | CMOS | — |
| Macro Cells | 192 | — |
| Usable Gates | 3,750 | 3,750 |
| User I/Os | 124 | — |
| Propagation Delay (tPD) | 7.5 ns | — |
| Internal Counter Frequency | 167 MHz | — |
| Pin Count | 160 | — |
| Package Type | PQFP (Plastic Quad Flat Pack) | — |
| Supply Voltage (VCCINT) | 5.0 V | 5.0 V |
| I/O Voltage (VCCIO) | 3.3 V / 5.0 V selectable | — |
| Programmability | EEPROM, In-System (JTAG ISP) | — |
| JTAG Support | IEEE 1149.1 Boundary Scan | — |
| Operating Temperature | 0 C to 70 C (Commercial) | [DATA_NEEDED: commercial/industrial grade] |
| Mounting Type | Surface Mount | Surface Mount |
| Lead-Free (Pb-Free) | Yes (N suffix) | — |
| RoHS Status | Compliant (Pb-free terminal finish) | [DATA_NEEDED: RoHS compliance status] |
| Series | — | MAX 7000S |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 192 |
| Logic Array Blocks (LABs) | — | 12 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Operating Frequency | — | 100 MHz |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| In-System Programmability | — | Yes (IEEE 1149.1 JTAG) |
| Package / Case | — | 160-BQFP (PQFP, 0.65 mm pitch) |