EPM7192SQI160-10N vs EPM7192SQC160-15 Comparison
Detailed side-by-side comparison of EPM7192SQI160-10N by Intel and EPM7192SQC160-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7192SQI160-10N | EPM7192SQC160-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Series | MAX 7000S | — |
| Family | MAX 7000 | MAX 7000S |
| Architecture | Second-generation MAX (CMOS, EEPROM) | — |
| Logic Elements / Macrocells | 192 macrocells | — |
| Usable Gates | 3.75K (typical) | — |
| User I/Os | 124 | — |
| Pin Count | 160 | — |
| Package | PQFP-160 (QFP-160, plastic) | PQFP-160 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency | 167 MHz | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| Supply Voltage (VCCIO) | 5.0 V | — |
| In-System Programmability | Yes (5V ISP, JTAG) | — |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) | — |
| Operating Temperature | 0C to +70C (industrial, 'N' suffix) | — |
| Mounting Type | Surface Mount | Surface Mount |
| Technology | 5V CMOS, EEPROM configuration memory | — |
| Logic Family | CMOS | — |
| Propagation Delay | 7.5 ns to 10 ns (speed grade dependent) | — |
| RoHS Status | Compliant (per lead-free PQFP package marking) | — |
| Device Type | — | CPLD - Complex Programmable Logic Device |
| Number of Macrocells | — | 192 |
| Number of Logic Array Blocks | — | 4 |
| Number of Usable Gates | — | 3750 |
| User I/O Pins | — | 124 |
| Pin-to-Pin Logic Delay (tPD) | — | 15 ns |
| Maximum Operating Frequency | — | 76.9 MHz |
| Supply Voltage | — | 5.0 V |
| Programmability | — | In-System (ISP) via JTAG IEEE Std 1149.1 |
| Configuration Memory | — | EEPROM, non-volatile |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |
| Process Technology | — | CMOS, EEPROM-based |