EPM7192SQI160-10N - MAX 7000S CPLD, 192 Macrocells, 100MHz | Altera
MPN: EPM7192SQI160-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $63.24 | $63.24 |
| 10 | $56.92 | $569.20 |
| 100 | $48.75 | $4,875.00 |
| 500 | $41.3 | $20,650.00 |
| 1,000 | $35.9 | $35,900.00 |
Drop-in alternatives for EPM7192SQI160-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM7192SQI160-10
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View Datasheet βEPM7192SQI160-10N Maximum Ratings & Electrical Characteristics
| Series | MAX 7000S |
| Family | MAX 7000 |
| Architecture | Second-generation MAX (CMOS, EEPROM) |
| Logic Elements / Macrocells | 192 macrocells |
| Usable Gates | 3.75K (typical) |
| User I/Os | 124 |
| Pin Count | 160 |
| Package | PQFP-160 (QFP-160, plastic) |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Maximum Internal Frequency | 167 MHz |
| Supply Voltage (VCCINT) | 5.0 V |
| Supply Voltage (VCCIO) | 5.0 V |
| In-System Programmability | Yes (5V ISP, JTAG) |
| Boundary-Scan Support | IEEE 1149.1 (JTAG) |
| Operating Temperature | 0C to +70C (industrial, 'N' suffix) |
| Mounting Type | Surface Mount |
| Technology | 5V CMOS, EEPROM configuration memory |
| Logic Family | CMOS |
| Propagation Delay | 7.5 ns to 10 ns (speed grade dependent) |
| RoHS Status | Compliant (per lead-free PQFP package marking) |
EPM7192SQI160-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (LAB I/O bank) |
| Pin 2 | I/O β User I/O pin (LAB I/O bank) |
| Pin 3 | I/O β User I/O pin (LAB I/O bank) |
| Pin 4 | I/O β User I/O pin (LAB I/O bank) |
| Pin 5 | I/O β User I/O pin (LAB I/O bank) |
| Pin 6 | I/O β User I/O pin (LAB I/O bank) |
| Pin 7 | I/O β User I/O pin (LAB I/O bank) |
| Pin 8 | I/O β User I/O pin (LAB I/O bank) |
| Pin 9 | I/O β User I/O pin (LAB I/O bank) |
| Pin 10 | I/O β User I/O pin (LAB I/O bank) |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin (LAB I/O bank) |
| Pin 13 | I/O β User I/O pin (LAB I/O bank) |
| Pin 14 | I/O β User I/O pin (LAB I/O bank) |
| Pin 15 | I/O β User I/O pin (LAB I/O bank) |
| Pin 16 | I/O β User I/O pin (LAB I/O bank) |
| Pin 17 | I/O β User I/O pin (LAB I/O bank) |
| Pin 18 | I/O β User I/O pin (LAB I/O bank) |
| Pin 19 | I/O β User I/O pin (LAB I/O bank) |
| Pin 20 | I/O β User I/O pin (LAB I/O bank) |
| Pin 21 | GND β Ground |
| Pin 22 | I/O β User I/O pin (LAB I/O bank) |
| Pin 23 | I/O β User I/O pin (LAB I/O bank) |
| Pin 24 | I/O β User I/O pin (LAB I/O bank) |
| Pin 25 | I/O β User I/O pin (LAB I/O bank) |
| Pin 26 | I/O β User I/O pin (LAB I/O bank) |
| Pin 27 | I/O β User I/O pin (LAB I/O bank) |
| Pin 28 | I/O β User I/O pin (LAB I/O bank) |
| Pin 29 | I/O β User I/O pin (LAB I/O bank) |
| Pin 30 | I/O β User I/O pin (LAB I/O bank) |
| Pin 31 | VCC β 5V supply (VCCIO) |
| Pin 32 | I/O β User I/O pin (LAB I/O bank) |
| Pin 33 | I/O β User I/O pin (LAB I/O bank) |
| Pin 34 | I/O β User I/O pin (LAB I/O bank) |
| Pin 35 | I/O β User I/O pin (LAB I/O bank) |
| Pin 36 | I/O β User I/O pin (LAB I/O bank) |
| Pin 37 | I/O β User I/O pin (LAB I/O bank) |
| Pin 38 | I/O β User I/O pin (LAB I/O bank) |
| Pin 39 | I/O β User I/O pin (LAB I/O bank) |
| Pin 40 | I/O β User I/O pin (LAB I/O bank) |
| Pin 41 | GND β Ground |
| Pin 42 | I/O β User I/O pin (LAB I/O bank) |
| Pin 43 | I/O β User I/O pin (LAB I/O bank) |
| Pin 44 | I/O β User I/O pin (LAB I/O bank) |
| Pin 45 | I/O β User I/O pin (LAB I/O bank) |
| Pin 46 | I/O β User I/O pin (LAB I/O bank) |
| Pin 47 | I/O β User I/O pin (LAB I/O bank) |
| Pin 48 | I/O β User I/O pin (LAB I/O bank) |
| Pin 49 | I/O β User I/O pin (LAB I/O bank) |
| Pin 50 | I/O β User I/O pin (LAB I/O bank) |
| Pin 51 | VCC β 5V supply (VCCIO) |
| Pin 52 | I/O β User I/O pin (LAB I/O bank) |
| Pin 53 | I/O β User I/O pin (LAB I/O bank) |
| Pin 54 | I/O β User I/O pin (LAB I/O bank) |
| Pin 55 | I/O β User I/O pin (LAB I/O bank) |
| Pin 56 | I/O β User I/O pin (LAB I/O bank) |
| Pin 57 | I/O β User I/O pin (LAB I/O bank) |
| Pin 58 | I/O β User I/O pin (LAB I/O bank) |
| Pin 59 | I/O β User I/O pin (LAB I/O bank) |
| Pin 60 | I/O β User I/O pin (LAB I/O bank) |
| Pin 61 | GND β Ground |
| Pin 62 | I/O β User I/O pin (LAB I/O bank) |
| Pin 63 | I/O β User I/O pin (LAB I/O bank) |
| Pin 64 | I/O β User I/O pin (LAB I/O bank) |
| Pin 65 | I/O β User I/O pin (LAB I/O bank) |
| Pin 66 | I/O β User I/O pin (LAB I/O bank) |
| Pin 67 | I/O β User I/O pin (LAB I/O bank) |
| Pin 68 | I/O β User I/O pin (LAB I/O bank) |
| Pin 69 | I/O β User I/O pin (LAB I/O bank) |
| Pin 70 | I/O β User I/O pin (LAB I/O bank) |
| Pin 71 | VCC β 5V supply (VCCINT) |
| Pin 72 | I/O β User I/O pin (LAB I/O bank) |
| Pin 73 | I/O β User I/O pin (LAB I/O bank) |
| Pin 74 | I/O β User I/O pin (LAB I/O bank) |
| Pin 75 | I/O β User I/O pin (LAB I/O bank) |
| Pin 76 | I/O β User I/O pin (LAB I/O bank) |
| Pin 77 | I/O β User I/O pin (LAB I/O bank) |
| Pin 78 | I/O β User I/O pin (LAB I/O bank) |
| Pin 79 | I/O β User I/O pin (LAB I/O bank) |
| Pin 80 | I/O β User I/O pin (LAB I/O bank) |
| Pin 81 | GND β Ground |
| Pin 82 | I/O β User I/O pin (LAB I/O bank) |
| Pin 83 | I/O β User I/O pin (LAB I/O bank) |
| Pin 84 | I/O β User I/O pin (LAB I/O bank) |
| Pin 85 | I/O β User I/O pin (LAB I/O bank) |
| Pin 86 | I/O β User I/O pin (LAB I/O bank) |
| Pin 87 | I/O β User I/O pin (LAB I/O bank) |
| Pin 88 | I/O β User I/O pin (LAB I/O bank) |
| Pin 89 | I/O β User I/O pin (LAB I/O bank) |
| Pin 90 | I/O β User I/O pin (LAB I/O bank) |
| Pin 91 | VCC β 5V supply (VCCIO) |
| Pin 92 | I/O β User I/O pin (LAB I/O bank) |
| Pin 93 | I/O β User I/O pin (LAB I/O bank) |
| Pin 94 | I/O β User I/O pin (LAB I/O bank) |
| Pin 95 | I/O β User I/O pin (LAB I/O bank) |
| Pin 96 | I/O β User I/O pin (LAB I/O bank) |
| Pin 97 | I/O β User I/O pin (LAB I/O bank) |
| Pin 98 | I/O β User I/O pin (LAB I/O bank) |
| Pin 99 | I/O β User I/O pin (LAB I/O bank) |
| Pin 100 | I/O β User I/O pin (LAB I/O bank) |
| Pin 101 | GND β Ground |
| Pin 102 | I/O β User I/O pin (LAB I/O bank) |
| Pin 103 | I/O β User I/O pin (LAB I/O bank) |
| Pin 104 | I/O β User I/O pin (LAB I/O bank) |
| Pin 105 | I/O β User I/O pin (LAB I/O bank) |
| Pin 106 | I/O β User I/O pin (LAB I/O bank) |
| Pin 107 | I/O β User I/O pin (LAB I/O bank) |
| Pin 108 | I/O β User I/O pin (LAB I/O bank) |
| Pin 109 | I/O β User I/O pin (LAB I/O bank) |
| Pin 110 | I/O β User I/O pin (LAB I/O bank) |
| Pin 111 | VCC β 5V supply (VCCINT) |
| Pin 112 | I/O β User I/O pin (LAB I/O bank) |
| Pin 113 | I/O β User I/O pin (LAB I/O bank) |
| Pin 114 | I/O β User I/O pin (LAB I/O bank) |
| Pin 115 | I/O β User I/O pin (LAB I/O bank) |
| Pin 116 | I/O β User I/O pin (LAB I/O bank) |
| Pin 117 | I/O β User I/O pin (LAB I/O bank) |
| Pin 118 | I/O β User I/O pin (LAB I/O bank) |
| Pin 119 | I/O β User I/O pin (LAB I/O bank) |
| Pin 120 | I/O β User I/O pin (LAB I/O bank) |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O pin (LAB I/O bank) |
| Pin 123 | I/O β User I/O pin (LAB I/O bank) |
| Pin 124 | I/O β User I/O pin (LAB I/O bank) |
| Pin 125 | I/O β User I/O pin (LAB I/O bank) |
| Pin 126 | I/O β User I/O pin (LAB I/O bank) |
| Pin 127 | I/O β User I/O pin (LAB I/O bank) |
| Pin 128 | I/O β User I/O pin (LAB I/O bank) |
| Pin 129 | I/O β User I/O pin (LAB I/O bank) |
| Pin 130 | I/O β User I/O pin (LAB I/O bank) |
| Pin 131 | VCC β 5V supply (VCCIO) |
| Pin 132 | I/O β User I/O pin (LAB I/O bank) |
| Pin 133 | I/O β User I/O pin (LAB I/O bank) |
| Pin 134 | I/O β User I/O pin (LAB I/O bank) |
| Pin 135 | I/O β User I/O pin (LAB I/O bank) |
| Pin 136 | I/O β User I/O pin (LAB I/O bank) |
| Pin 137 | I/O β User I/O pin (LAB I/O bank) |
| Pin 138 | I/O β User I/O pin (LAB I/O bank) |
| Pin 139 | I/O β User I/O pin (LAB I/O bank) |
| Pin 140 | I/O β User I/O pin (LAB I/O bank) |
| Pin 141 | GND β Ground |
| Pin 142 | I/O β User I/O pin (LAB I/O bank) |
| Pin 143 | I/O β User I/O pin (LAB I/O bank) |
| Pin 144 | I/O β User I/O pin (LAB I/O bank) |
| Pin 145 | I/O β User I/O pin (LAB I/O bank) |
| Pin 146 | I/O β User I/O pin (LAB I/O bank) |
| Pin 147 | I/O β User I/O pin (LAB I/O bank) |
| Pin 148 | I/O β User I/O pin (LAB I/O bank) |
| Pin 149 | I/O β User I/O pin (LAB I/O bank) |
| Pin 150 | I/O β User I/O pin (LAB I/O bank) |
| Pin 151 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 152 | TMS β JTAG Test Mode Select |
| Pin 153 | TCK β JTAG Test Clock |
| Pin 154 | TDO β JTAG Test Data Out |
| Pin 155 | NC β Not connected (per datasheet) |
| Pin 156 | NC β Not connected (per datasheet) |
| Pin 157 | GND β Ground |
| Pin 158 | OE1 β Output Enable 1 (global) |
| Pin 159 | OE2/GCLK2 β Output Enable 2 / Global Clock 2 |
| Pin 160 | GCLK1 β Global Clock 1 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM7192SQI160-10N is suitable for 6 applications: Industrial Bus Address Decoding, PCI Bridge Glue Logic, Motor Control Sequencing, Legacy 5V System Glue Logic, Telecom Backplane Buffering, Test & Measurement Front-End.
Industrial Bus Address Decoding
The EPM7192SQI160-10N's 192 macrocells and 124 user I/Os make it well suited to industrial bus address decoding where multiple peripherals share an address-mapped bus such as ISA, PC/104, or legacy VME. The 10 ns pin-to-pin delay guarantees deterministic address-to-chip-select latency, which is critical when a single CPLD must decode dozens of peripheral windows in real time. With EEPROM-based non-volatile configuration, the decoder powers up fully active - no boot ROM is needed and there is no FPGA-style configuration delay that could miss the first bus cycles. Industrial PLC backplanes and process-control cards can drop this part into a PQFP-160 socket and immediately gain reliable address-decoding glue logic.
Recommended
PCI Bridge Glue Logic
Legacy PCI adapter cards and embedded PCI bridges use the EPM7192SQI160-10N to implement hot-plug control signals, interrupt steering, and arbitration glue. The 124 user I/Os comfortably route the full complement of PCI sideband signals (PERR, SERR, STOP, DEVSEL, TRDY, IRDY) plus local-bus interface signals, while the 10 ns delay meets PCI 33 MHz setup/hold budgets. Its 5V-tolerant I/Os allow direct interfacing with classic 5V PCI slots without external transceivers. The non-volatile EEPROM bitstream lets a PCI card enumerate immediately at power-on without BIOS-side configuration overhead.
Recommended
Motor Control Sequencing
Stepper and brushless DC motor controllers benefit from the EPM7192SQI160-10N's deterministic state-machine execution and 167 MHz internal counter frequency, which are ideal for generating commutation waveforms, PWM gating signals, and encoder decoding in real time. The 192 macrocells can host multiple parallel state machines - one for each motor axis - while the 124 I/Os drive H-bridge enable lines, current-sense comparators, and Hall-effect sensor inputs without external muxing. The 5V CMOS outputs interface directly to industry-standard gate drivers, eliminating level shifters in 24V industrial motion systems.
Recommended
Legacy 5V System Glue Logic
The EPM7192SQI160-10N shines in legacy 5V systems - such as industrial controllers, test equipment, and avionics retrofit boards - where replacing discrete 74LS/74F glue with one CPLD reduces board area and improves reliability. Its 5.0V VCCINT and VCCIO rails connect directly to existing 5V power planes, and its 124 I/Os replace dozens of discrete AND/OR gates, latches, and decoder chips. The non-volatile configuration survives brown-out events that would otherwise wipe an SRAM-based FPGA, and JTAG boundary scan supports legacy manufacturing-test infrastructure built around IEEE 1149.1.
Recommended
Telecom Backplane Buffering
Central-office telecom equipment frequently relies on the EPM7192SQI160-10N as a backplane buffer and protocol-translation device between T1/E1 framers, HDLC controllers, and TDM switching fabrics. The 10 ns propagation delay preserves tight timing margins on backplane traces, while the 5V I/Os drive the long, terminated buses typical of telecom shelves. In-system programmability allows field upgrades over JTAG without removing line cards, and 124 I/Os handle 8-bit parallel TDM buses plus framing and clock-distribution signals without external mux logic.
Recommended
Test & Measurement Front-End
Bench-top test instruments and ATE (Automatic Test Equipment) fixtures use the EPM7192SQI160-10N to implement pin-electronics drivers, pattern-generation sequencers, and timing-edge generators with deterministic latency. The 10 ns tPD is fast enough for sub-100 MHz digital test patterns, and the 124 I/Os route enough channels to drive a moderate-density test head. JTAG-based ISP lets fixture designers update the test pattern over USB-Blaster or ByteBlaster without disassembling the fixture - critical in production ATE environments.
Recommended
Recommended Products Summary
Engineering reference data for EPM7192SQI160-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM7192SQI160-10 | EPM7192SQC160-10N | EPM7192SQC160-15 | EPM7192SQC160-7N | EPM7192SQC160-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | PQFP-160 | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same | PQFP-160 - same |
| Macrocells | 192 | 192 | 192 | 192 | 192 | 192 |
| User I/Os | 124 | 124 | 124 | 124 | 124 | 124 |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 15 ns | 7 ns | 10 ns |
| Internal Frequency | 167 MHz | 167 MHz | 167 MHz | 125 MHz | 175.4 MHz | 167 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Operating Temperature | 0C to 70C (industrial, 'N') | 0C to 70C (commercial) | 0C to 70C (industrial) | 0C to 70C (commercial) | 0C to 70C (industrial) | 0C to 70C (commercial) |
| Approx. Unit Price (USD, as of 2026-09-13) | $63.24 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest-density 5V MAX 7000S with 124 user I/Os (vs EPM7192SQC160-10N)
- Same PQFP-160 footprint across the entire MAX 7192 family (vs EPM7192SQC160-15)
- Drop-in speed-grade upgrade path (vs EPM7192SQC160-7N)
Design Notes
The EPM7192SQI160-10N requires a tightly regulated 5.0V supply on VCCINT and VCCIO pins. Place 0.1uF decoupling capacitors as close as practical to each VCC pin and bulk 10uF tantalum or ceramic caps near the package corners. Avoid powering the device from a switching regulator without adequate filtering - the 5V EEPROM charge pump can inject noise into the logic supply and cause ISP programming failures or marginal timing.
The PQFP-160 package has 0.5 mm pitch leads that demand a 4-layer PCB with a solid ground plane directly under the device. Keep high-speed traces on the opposite side and use 0.2 mm / 8 mil trace-and-space for fan-out. Provide a continuous thermal copper pour under the PQFP body (the package is plastic so thermal dissipation is moderate but a copper island reduces junction-to-ambient thermal resistance).
Do not confuse the EPM7192SQI160-10N (industrial 0C-70C, 'N' suffix) with the EPM7192SQI160-10 (commercial). Both are PQFP-160 and pin-compatible, but the device ID differs and existing Quartus / MAX+PLUS II project files targeting the -10 may need recompilation for the -10N silicon. Also verify the JTAG chain order - the EPM7192SQI160-10N TDI/TMS/TCK/TDO pin locations follow the datasheet, and swapping in a faster -7 speed grade without recompiling may change BSDL behavior.
Although the 5V CMOS I/Os are robust, place 22-33 ohm series-termination resistors on clock outputs (GCLK1, GCLK2/OE2) if the trace length exceeds 50 mm to prevent ringing on fast edges. For high-fanout signals (chip selects, OE, GCLK), use a clock-buffer tree rather than a single output driving multiple loads, since the EPM7192SQI160-10N I/O drive strength is specified for moderate loads only.
Compliance Information
RoHS compliance per lead-free PQFP-160 package marking. The part is not AEC-Q100 qualified (industrial grade only). REACH and conflict-minerals compliance per Intel/Altera product environmental reports.
