EPM7256AETC100-10N vs EPM7256AETC100-7 Comparison

Detailed side-by-side comparison of EPM7256AETC100-10N by Altera and EPM7256AETC100-7 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM7256AETC100-10N EPM7256AETC100-7
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Stock Status In Stock In Stock
Unit Price (USD) $13.10 $10.45
Family MAX 7000A MAX 7000A
Device Type CPLD (Complex Programmable Logic Device) CPLD - Complex Programmable Logic Device
Macro Cells 256 β€”
Usable Gates 5,000 5,000
Maximum User I/Os 84 β€”
Logic Elements / LABs 16 Logic Array Blocks β€”
Pin-to-Pin Logic Delay 10 ns β€”
Maximum Operating Frequency 125 MHz 126.6 MHz
Supply Voltage (Core) 3.3 V β€”
MultiVolt I/O Support 2.5 V / 3.3 V / 5.0 V β€”
Programmability EEPROM, in-system via JTAG (IEEE 1149.1) β€”
Package 100-pin TQFP TQFP-100 (ET100)
Mounting Type Surface Mount Surface Mount
Operating Temperature Range 0C to +70C (commercial) [DATA_NEEDED: explicit grade from datasheet] β€”
Process Technology 0.30 Β΅m EEPROM β€”
Dedicated Inputs 4 (global clock / clear / OE) β€”
RoHS Status [DATA_NEEDED: not confirmed in provided data] Unknown - part marked obsolete
Lead-Free / Pb-Free [DATA_NEEDED: not confirmed in provided data] β€”
Series β€” EPM7256
Technology β€” EEPROM-based, CMOS
Macrocells β€” 256
Number of I/Os β€” 84
Number of Logic Array Blocks (LABs) β€” 16
Core Supply Voltage β€” 3.3 V
Pin-to-Pin Delay (tPD) β€” 7.5 ns
Operating Temperature β€” 0C to +70C (Commercial)
Programming Interface β€” JTAG (IEEE 1149.1) - In-System Programmable
Memory Type β€” EEPROM (non-volatile)

Datasheets & Resources

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