EPM7256SQC208-10 vs EPM7256SQC208-15N Comparison
Detailed side-by-side comparison of EPM7256SQC208-10 by Intel and EPM7256SQC208-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7256SQC208-10 | EPM7256SQC208-15N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Type | Complex Programmable Logic Device (CPLD) | — |
| Family / Series | MAX 7000 | — |
| Macrocells | 256 | 256 |
| Logic Array Blocks (LABs) | 16 | — |
| Usable Gates | 5000 | — |
| User I/O Pins | 164 | 164 |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns | — |
| Supply Voltage | 5.0 V | 5 V |
| Configuration Technology | EEPROM | — |
| Package | 208-pin PQFP | 208-pin PQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature Range | [DATA_NEEDED: operating temperature range] | — |
| JTAG Support | IEEE 1149.1 boundary-scan | — |
| In-System Programmability | Yes (ISP) | Yes (ISP) |
| RoHS Status | [DATA_NEEDED: RoHS status] | Lead free / RoHS Compliant |
| Moisture Sensitivity Level (MSL) | [DATA_NEEDED: MSL level] | — |
| Speed Grade | -10 (10 ns) | -15 |
| Series | — | MAX 7000S |
| Pin-to-Pin Delay | — | 15 ns (speed grade -15) |
| Configuration Memory | — | EEPROM (non-volatile) |
| JTAG Interface | — | IEEE 1149.1 boundary-scan |
| Operating Temperature | — | [DATA_NEEDED: operating temperature range] |
| Logic Array Blocks | — | 16 macrocells per LAB |
| Interconnect | — | Programmable Interconnect Array (PIA) |
| Product Category | — | CPLD - Complex Programmable Logic Devices |
| Manufacturer | — | Altera (Intel Programmable Solutions Group) |