EPM7256SRC208-15N vs EPM7256SQC208-10 Comparison
Detailed side-by-side comparison of EPM7256SRC208-15N by Altera and EPM7256SQC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM7256SRC208-15N | EPM7256SQC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Series | MAX 7000S | — |
| Macrocells | 256 | 256 |
| Usable Gates | 5,000 | 5000 |
| User I/O Pins | 164 | 164 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Pin-to-Pin Delay (tPD) | 15 ns | — |
| Maximum Counter Frequency | 76.9 MHz | — |
| Supply Voltage | 5 V | 5.0 V |
| Configuration Memory | EEPROM (non-volatile) | — |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin PQFP |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | Yes (ISP) |
| I/O Standard | 5 V TTL/CMOS compatible | — |
| RoHS Status | Compliant (N suffix) | [DATA_NEEDED: RoHS status] |
| Lead Free | Yes (N suffix) | — |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Number of Terminals | 208 | — |
| Device Type | — | Complex Programmable Logic Device (CPLD) |
| Family / Series | — | MAX 7000 |
| Pin-to-Pin Propagation Delay (tPD) | — | 10 ns |
| Configuration Technology | — | EEPROM |
| Operating Temperature Range | — | [DATA_NEEDED: operating temperature range] |
| JTAG Support | — | IEEE 1149.1 boundary-scan |
| Moisture Sensitivity Level (MSL) | — | [DATA_NEEDED: MSL level] |
| Speed Grade | — | -10 (10 ns) |