EPM9320ALC84-10 vs EPM9320ALC84-20 Comparison

Detailed side-by-side comparison of EPM9320ALC84-10 by Intel and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320ALC84-10 EPM9320ALC84-20
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $19.80 $10.50
Family MAX 9000 MAX 9000
Device EPM9320 β€”
Macrocells 320 320
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 52 β€”
Dedicated Inputs 16 β€”
Speed Grade -10 (10 ns pin-to-pin delay) β€”
Pin-to-Pin Delay (tPD) 10 ns 20 ns
Supply Voltage (VCCINT) 5.0 V β€”
In-System Programmability 5.0 V ISP via IEEE 1149.1 JTAG β€”
Technology CMOS EEPROM-based, third-generation MAX β€”
PCI Compliance PCI Local Bus Specification Rev. 2.2 (speed grade -10) β€”
Package 84-pin PLCC (J-Lead) PLCC-84
Operating Temperature [DATA_NEEDED: commercial/industrial grade] [DATA_NEEDED: commercial or industrial grade]
Mounting Type Surface Mount / Through-Hole (PLCC socket) Surface Mount (PLCC socket compatible)
RoHS Status [DATA_NEEDED] [DATA_NEEDED: per Altera datasheet]
Non-Volatile Configuration Yes (EEPROM cell, powers up in known state) β€”
Architecture MAX (Multiple Array MatriX) with FastTrack Interconnect β€”
Device Type β€” EPLD (Erasable Programmable Logic Device)
Maximum User I/Os β€” 212
Process Technology β€” 0.5 Β΅m CMOS EEPROM
Supply Voltage β€” 5.0 V
Programmability β€” In-system via IEEE 1149.1 JTAG
Configuration Memory β€” Non-volatile EEPROM
Boundary Scan β€” JTAG IEEE 1149.1
Design Software β€” MAX+PLUS II / Quartus II (legacy)

Datasheets & Resources

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