EPM9320ALC84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel
MPN: EPM9320ALC84-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.65 | $346.50 |
| 100 | $28.4 | $2,840.00 |
| 500 | $23.75 | $11,875.00 |
| 1,000 | $19.8 | $19,800.00 |
Drop-in alternatives for EPM9320ALC84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320ALI84-10
β Drop-Inβ In Stock
$19.95 / Unit
View Datasheet βEPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320LC84-10
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$84.96 / Unit
View Datasheet βEPM9320ALC84-10N
β Drop-Inβ In Stock
$21.4 / Unit
View Datasheet βEPM9320ALC84-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device | EPM9320 |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 52 |
| Dedicated Inputs | 16 |
| Speed Grade | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 5.0 V |
| In-System Programmability | 5.0 V ISP via IEEE 1149.1 JTAG |
| Technology | CMOS EEPROM-based, third-generation MAX |
| PCI Compliance | PCI Local Bus Specification Rev. 2.2 (speed grade -10) |
| Package | 84-pin PLCC (J-Lead) |
| Mounting Type | Surface Mount / Through-Hole (PLCC socket) |
| Non-Volatile Configuration | Yes (EEPROM cell, powers up in known state) |
| Architecture | MAX (Multiple Array MatriX) with FastTrack Interconnect |
EPM9320ALC84-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (Macrocells / LAB interconnect) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | VCCINT β 5.0 V core supply |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | TDI β JTAG Test Data In |
| Pin 15 | TMS β JTAG Test Mode Select |
| Pin 16 | TCK β JTAG Test Clock |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | VCCIO β 5.0 V I/O supply |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | VCCINT β 5.0 V core supply |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | GND β Ground |
| Pin 42 | INPUT/GCLK β Dedicated input / Global Clock |
| Pin 43 | INPUT/GCLK β Dedicated input / Global Clock |
| Pin 44 | INPUT/GCLK β Dedicated input / Global Clock |
| Pin 45 | INPUT β Dedicated input pin |
| Pin 46 | INPUT β Dedicated input pin |
| Pin 47 | INPUT β Dedicated input pin |
| Pin 48 | INPUT β Dedicated input pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | VCCIO β 5.0 V I/O supply |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | GND β Ground |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | VCCINT β 5.0 V core supply |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | I/O β User I/O pin |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ALC84-10 is suitable for 6 applications: PCI Bus Interface Glue Logic, Embedded Microprocessor Peripheral Controller, Bus Protocol Translation Bridge, Industrial Control State Machine, Legacy 5V System Glue Logic, Field-Upgradeable Control Plane.
PCI Bus Interface Glue Logic
The EPM9320ALC84-10 fits PCI bus interface designs because its -10 speed grade is explicitly compliant with PCI Local Bus Specification Revision 2.2, providing the required AC switching characteristics at 33 MHz. With 320 macrocells and 16 dedicated inputs, the device can implement address decoding, command decoding, and interrupt steering across multiple bus slots in a single chip. The 52 user I/O pins support 32-bit data plus control signals, and the 10 ns tPD ensures deterministic timing across the central FastTrack Interconnect.
Recommended
Embedded Microprocessor Peripheral Controller
With 320 macrocells, 5.0-V I/O, and JTAG ISP, the EPM9320ALC84-10 fits 8051, x86, or 68k embedded systems that need deterministic peripheral glue logic. The MAX architecture's central FastTrack Interconnect gives predictable tPD, and the non-volatile EEPROM cell eliminates external boot PROMs, simplifying board bring-up. The 84-PLCC package supports socketed prototypes and field upgrades via JTAG, and the 5.0-V tolerance matches TTL logic in industrial 5-V backplanes.
Recommended
Bus Protocol Translation Bridge
The EPM9320ALC84-10 implements ISA-to-PCI, VME-to-PCI, or PC/104-to-PCI protocol bridges because of its high macrocell count (320), 10 ns tPD, and 52 user I/O pins. A bridge can use LABs for state-machine protocol engines, with the central interconnect carrying control signals between LABs at deterministic delay. The 5.0-V I/O matches legacy 5-V buses directly, and JTAG ISP lets designers field-upgrade protocol firmware without removing the part from the socket.
Recommended
Industrial Control State Machine
For factory automation, motor control sequencers, and PLC digital sub-systems, the EPM9320ALC84-10 offers the deterministic timing, 5.0-V I/O, and wide temperature operation (via the -I suffix variant) required for industrial environments. The 320 macrocells can encode multi-state control loops, fault-handling state machines, and timing generators in a single device. The MAX 9000 architecture's wide Product-Term allocation supports large fan-in logic, useful for combining sensor inputs into control outputs.
Recommended
Legacy 5V System Glue Logic
The EPM9320ALC84-10 is purpose-designed for 5-V backplanes, VMEbus, and 5-V PCI systems where 3.3-V or 1.8-V FPGAs cannot interface directly. With 5.0-V VCCINT, 5.0-V tolerant I/O, and 5.0-V ISP via JTAG, it replaces dozens of 74-series TTL glue chips with a single programmable part. Designers use the 320 macrocells to consolidate address decoders, chip-select generators, interrupt arbiters, and bus transceivers - simplifying PCB layout and reducing BOM cost in legacy systems.
Recommended
Field-Upgradeable Control Plane
Designers deploy the EPM9320ALC84-10 in field-upgradeable control planes where the 5.0-V ISP via JTAG allows remote firmware updates without board removal. The non-volatile EEPROM cell ensures the device powers up in a known state even after power-cycling, and the JTAG interface can be reused for boundary-scan testing during manufacturing. Combined with the 84-PLCC socket, this enables field serviceability for telecom, aerospace, and defense systems where board swap-out is expensive.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ALC84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ALI84-10 | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320ALC84-10N | EPM9320ARC208-10 |
|---|---|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 208-pin RQFP/PQFP - DIFFERENT |
| Speed Grade (tPD) | 10 ns | 10 ns | 15 ns (-50%) | 10 ns | 10 ns | 10 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Logic Array Blocks (LABs) | 16 | 16 | 16 | 16 | 16 | 16 |
| Maximum User I/O | 52 | 52 | 52 | 52 | 52 | higher (~132 in 208-pin) |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Temperature Grade | Commercial (0C to +70C) | Industrial (-40C to +85C) | Commercial | Commercial | Commercial | Commercial |
| PCI 2.2 Compliance | Yes (speed grade -10) | Yes (speed grade -10) | Not for -15 speed grade | Yes (speed grade -10) | Yes | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Highest speed grade in MAX 9000 family for PCI 2.2 compliance (vs EPM9320LC84-15)
- 320 macrocells - largest density in MAX 9000 PLCC line (vs EPM7256SRC208-10)
- 84-PLCC package suitable for socketed field upgrades (vs EPM9320ARC208-10)
Design Notes
The EPM9320ALC84-10 requires a stable 5.0 V supply on VCCINT and VCCIO pins. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the package pin, plus a bulk 10-47 uF tantalum or electrolytic capacitor at the board supply entry. The device draws typical ICC in the 100-300 mA range during operation, depending on toggle frequency; consult the MAX 9000 family datasheet Power Consumption vs. Frequency graph. Estimated: with 50% I/O toggle at 33 MHz and all 320 macrocells enabled, ICC may approach 250 mA - derate the supply accordingly.
Place a JTAG header (TCK, TMS, TDI, TDO, GND, VCC) near the device for in-system programming. The 84-PLCC socket should be a low-profile machined-pin type to ensure reliable JTAG ISP contact. Route TCK with a ground guard trace to avoid JTAG communication errors, and keep JTAG traces short (<50 mm). For high-noise environments, add 10 kohm pull-ups on TMS and TDI to keep the JTAG state machine in a known reset state during power-up.
Assign high-speed clocks to dedicated INPUT/GCLK pins (pins 42-44 in 84-PLCC) to drive the global clock network with minimum skew. Reserve a separate ground plane under the PLCC socket for low-impedance return paths, and route 5.0-V VCCIO with at least 0.5 mm trace width to limit voltage drop. For PCI bus designs, match trace lengths within the 2.5 ns PCI 2.2 spec; the -10 speed grade gives 10 ns tPD, leaving margin for interconnect delay.
Do not apply 3.3-V signals directly to the EPM9320ALC84-10 I/O - it is a 5.0-V-only device and signals above VCCIO + 0.5 V can damage input structures. Use a level shifter or buffer when interfacing to 3.3-V logic. Additionally, the JTAG TCK must not exceed 10 MHz for reliable ISP operation; if faster programming is required, use the parallel ByteBlasterMV or USB-Blaster download cable. Always issue the BYPASS instruction before powering down to avoid spurious JTAG state machine transitions.
Compliance Information
Compliance data not in the verified web data sources. The EPM9320ALC84-10N variant indicates lead-free (Pb-free) reflow compatibility per Intel/Altera naming convention. RoHS and REACH status to be verified against the manufacturer datasheet before new designs.
