EPM9320ALC84-10N vs EPM9320ALC84-20 Comparison
Detailed side-by-side comparison of EPM9320ALC84-10N by Intel and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALC84-10N | EPM9320ALC84-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Series | MAX 9000A | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Number of Macrocells | 320 | — |
| Number of Gates | 6,000 | — |
| Number of Logic Array Blocks (LABs) | 16 | — |
| User I/O Pins | 60 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Internal Frequency (fCNT) | 144.9 MHz | — |
| Supply Voltage (VCC) | 5.0 V nominal | — |
| Operating Temperature Range | 0C to +70C (Commercial) | — |
| Programmable Technology | EEPROM (in-system programmable) | — |
| Programming Interface | JTAG (IEEE 1149.1) | — |
| Package | 84-Pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 |
| Mounting Type | Through-Hole / Socket | Surface Mount (PLCC socket compatible) |
| Part Status | Obsolete | — |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Process Technology | — | 0.5 µm CMOS EEPROM |
| Supply Voltage | — | 5.0 V |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Operating Temperature | — | [DATA_NEEDED: commercial or industrial grade] |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |
| RoHS Status | — | [DATA_NEEDED: per Altera datasheet] |