EPM9320ALC84-10N - 320-Macrocell MAX 9000 CPLD, 10ns, 84-PLCC
MPN: EPM9320ALC84-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.95 | $2,895.00 |
| 500 | $24.6 | $12,300.00 |
| 1,000 | $21.4 | $21,400.00 |
Drop-in alternatives for EPM9320ALC84-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320ALC84-10
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9320ALI84-10
β Drop-Inβ In Stock
$19.95 / Unit
View Datasheet βEPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320LC84-20
β Drop-Inβ In Stock
$9.75 / Unit
View Datasheet βEPM9320LI84-20
β Drop-Inβ In Stock
$12.8 / Unit
View Datasheet βEPM9320ALC84-10N Maximum Ratings & Electrical Characteristics
| Series | MAX 9000A |
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Number of Macrocells | 320 |
| Number of Gates | 6,000 |
| Number of Logic Array Blocks (LABs) | 16 |
| User I/O Pins | 60 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Internal Frequency (fCNT) | 144.9 MHz |
| Supply Voltage (VCC) | 5.0 V nominal |
| Operating Temperature Range | 0C to +70C (Commercial) |
| Programmable Technology | EEPROM (in-system programmable) |
| Programming Interface | JTAG (IEEE 1149.1) |
| Package | 84-Pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Through-Hole / Socket |
| Part Status | Obsolete |
EPM9320ALC84-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (function depends on user design) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | VCC β 5.0 V supply voltage |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground reference |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | TMS β JTAG Test Mode Select |
| Pin 16 | TCK β JTAG Test Clock |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | VCC β 5.0 V supply voltage |
| Pin 23 | GND β Ground reference |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | GCLK β Global Clock input |
| Pin 30 | GCLR β Global Clear input |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | OE1 β Output Enable (global) |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | GND β Ground reference |
| Pin 38 | VCC β 5.0 V supply voltage |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | OE2 β Output Enable (global) |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | VCC β 5.0 V supply voltage |
| Pin 52 | GND β Ground reference |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | TDI β JTAG Test Data In |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | VCC β 5.0 V supply voltage |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | TDO β JTAG Test Data Out |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | GND β Ground reference |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ALC84-10N is suitable for 6 applications: Legacy Industrial Control Boards, Telecom Line-Card Glue Logic, Address Decoding and Chip-Select Generation, Peripheral Bus Interfacing (ISA / PCI / VME), Motor-Control State Machines, Retrofit and Repair of Legacy Equipment.
Legacy Industrial Control Boards
The EPM9320ALC84-10N is widely deployed in legacy industrial control boards where its 320 macrocells and 60 I/O pins provide ample capacity for PLC-style glue logic, sensor multiplexing, and actuator control sequencing. With a deterministic 10 ns tPD and 5 V I/O tolerance, it directly interfaces to 5 V TTL/CMOS peripherals, encoder inputs, and opto-isolated feedback lines without level shifters. The 84-PLCC socketed package allows field-replacement on existing backplanes, minimizing downtime for retrofit programs in factory automation lines that have been in service for 15-20 years or longer.
Recommended
Telecom Line-Card Glue Logic
In telecom line-card and central-office equipment, the EPM9320ALC84-10N serves as deterministic glue logic between framer ICs, TDM switches, and backplane transceivers. Its 144.9 MHz fCNT supports 8 kHz/16 kHz/32 kHz time-slot framing alongside higher-speed E1/T1 clock recovery schemes, while the predictable PIA-based interconnect ensures zero-jitter output timing critical for PDH and SDH tributaries. The JTAG interface enables board-level boundary-scan testing during manufacture and field diagnostics, satisfying the IEEE 1149.1 testability mandates common in telecom-grade hardware. Obsolescence remains a key concern, so redesign programs target MAX II/MAX V equivalents.
Recommended
Address Decoding and Chip-Select Generation
The EPM9320ALC84-10N is ideally suited for memory and peripheral address decoding on legacy microprocessor boards, generating chip-select signals for SRAM, ROM, and I/O peripherals from a wide address bus. With 10 ns tPD, it produces clean chip-select pulses well within one clock cycle of 25-50 MHz 80x86, 68k, or PowerPC host buses. The 320 macrocells comfortably handle 16-to-24-bit address decoding with multiple active-low and active-high outputs, and the in-system programmability lets engineers iterate decoder maps during prototype without re-spinning the PCB. This application is one of the most common uses for the MAX 9000 family.
Recommended
Peripheral Bus Interfacing (ISA / PCI / VME)
The EPM9320ALC84-10N acts as a bus-interface bridge between legacy ISA, VME, and simple PCI target peripherals. It implements bus-state decoders, hand-shake sequencers, and interrupt controllers with deterministic 10 ns response, eliminating wait-state unpredictability from discrete TTL logic. The 5 V tolerant I/O connects directly to bus transceivers, while 60 user I/O pins handle address, data steering, and control signal multiplexing. The 84-PLCC socket allows engineers to swap parts for speed-grade upgrades or logic revisions during board bring-up without reworking the PCB.
Recommended
Motor-Control State Machines
The EPM9320ALC84-10N implements multi-axis stepper and BLDC motor control state machines by sequencing PWM generators, decoding Hall-sensor or quadrature-encoder feedback, and arbitrating direction/inhibit signals. The 10 ns tPD enables sub-microsecond control-loop updates at 50-100 kHz PWM rates, and the 60 user I/O pins handle multiple axes (typically 3-4 steppers or 2 BLDC motors) from a single device. EEPROM-based configuration retains state machine tables across power cycles, and the JTAG interface supports in-circuit debugging via Altera MAX+PLUS II or Quartus signal-tap logic.
Recommended
Retrofit and Repair of Legacy Equipment
The EPM9320ALC84-10N is primarily sourced today to repair and extend the service life of legacy equipment originally designed in the late 1990s and early 2000s. Medical imaging systems, military radios, industrial CNC controllers, and avionics subsystems all depend on the MAX 9000 family's reliability and 5 V tolerance. The PLCC socket mounting is critical here - it allows technicians to swap parts without specialized rework tools, even in field-deployed units. Authorized obsolete-part brokers maintain traceability documentation (date code, lot, original manufacturer) required by aerospace and medical OEM service contracts.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ALC84-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ALC84-10 | EPM9320ALI84-10 | EPM9320LC84-15 | EPM9320LC84-20 |
|---|---|---|---|---|---|
| Package | 84-PLCC | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same | 84-PLCC - same |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Supply Voltage (VCC) | 5.0 V | 5.0 V | 5.0 V | 3.3 V | 3.3 V |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 10 ns | 15 ns | 20 ns |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| User I/O | 60 | 60 | 60 | 60 | 60 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Industrial temperature variant available in same package (vs EPM9320ALI84-10)
- 3.3 V variant enables mixed-voltage system integration (vs EPM9320LC84-15)
- Identical die in alternative packaging (vs EPM9320ALC84-10)
Design Notes
The EPM9320ALC84-10N requires a stable 5.0 V VCC supply with a tolerance of +/-5% (4.75 V to 5.25 V). Place a 0.1 uF decoupling capacitor within 50 mils of each VCC pin (the 84-PLCC has multiple VCC and GND pins distributed around the package) to minimize ground bounce and VCC sag during simultaneous switching of high-fanout outputs. Bulk decoupling of 10-47 uF tantalum or aluminum polymer is recommended at the board-level power entry to the device's VCC rail.
The 84-PLCC package is a through-hole socket-mount part. Use a high-quality machined-pin PLCC socket (3M, Mill-Max, or equivalent) rated for the operating temperature range, especially for industrial and military designs. Avoid low-cost stamped sockets which may lose contact after thermal cycling. The PLCC socket footprint must accommodate the J-lead geometry - refer to the JEDEC MO-047 package outline for recommended land pattern dimensions.
Do not confuse the A-suffix (5 V VCC) EPM9320ALC84-10N with the L-suffix (3.3 V VCC) EPM9320LC84-15/20. Applying 5 V to a 3.3 V L-variant will permanently damage the device. The 'A' and 'L' letters in the Altera MAX 9000 nomenclature encode the voltage class, and engineers upgrading or downgrading designs must verify both the voltage and speed-grade suffixes. The 'N' suffix indicates tape-and-reel packaging versus tray.
Route JTAG signals (TMS, TCK, TDI, TDO) as short, parallel traces with a ground return path to avoid crosstalk. Place a 10 kohm pull-up on TCK and TMS to prevent floating inputs that may inadvertently trigger JTAG state-machine transitions. If the device is part of a multi-device JTAG chain, include 4.7 kohm series termination resistors on TDI/TDO between adjacent devices to dampen reflections on longer chains (>6 inches).
Compliance Information
MAX 9000 family parts from this generation typically use tin-lead (SnPb) PLCC leads and are not RoHS-compliant. Lead-free variants carry the 'N' or other suffix. For new RoHS-compliant designs, modern MAX II/MAX V/MAX 10 CPLD families should be evaluated.
